Module Definition
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Module : prim_sha2_pad
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.55 95.00 90.77 53.33 83.10

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad 80.55 95.00 90.77 53.33 83.10



Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.55 95.00 90.77 53.33 83.10


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.55 95.00 90.77 53.33 83.10


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.81 98.64 94.29 90.00 92.31 gen_multimode_logic.u_prim_sha2_multimode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sha2_pad
Line No.TotalCoveredPercent
TOTAL12011495.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6311100.00
ALWAYS6833100.00
ALWAYS83232295.65
ALWAYS17233100.00
ALWAYS178696594.20
ALWAYS32210990.00
ALWAYS34033100.00
CONT_ASSIGN34411100.00
ALWAYS34933100.00
CONT_ASSIGN35411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
53 1 1
57 1 1
63 1 1
68 2 2
69 1 1
83 1 1
85 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
99 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
115 0 1
119 1 1
123 1 1
130 1 1
141 1 1(1 unreachable)
MISSING_ELSE
172 2 2
173 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
184 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
192 1 1
197 1 1
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
209 1 1
212 1 1
213 1 1
214 1 1
215 1 1
217 1 1
218 1 1
219 1 1
220 1 1
225 1 1
226 1 1
227 1 1
233 1 1
234 1 1
235 1 1
239 1 1
240 1 1
241 1 1
243 1 1
244 1 1
273 1 1
274 1 1
276 1 1
277 1 1
278 2 2
279 1 1
281 1 1
286 1 1
287 1 1
289 1 1
290 1 1
291 1 1
293 0 1
294 0 1
299 1 1
300 1 1
302 1 1
303 1 1
304 1 1
306 0 1
307 0 1
316 2 2
317 2 2
MISSING_ELSE
322 1 1
324 1 1
326 1 1
327 1 1
329 0 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
==> MISSING_ELSE
MISSING_ELSE
340 2 2
341 1 1
344 1 1
349 2 2
350 1 1
354 1 1


Cond Coverage for Module : prim_sha2_pad
TotalCoveredPercent
Conditions13011890.77
Logical13011890.77
Non-Logical00
Event00

 LINE       45
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       57
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       94
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       94
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       188
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       198
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       209
 EXPRESSION (((tx_count == message_length_i) & MultimodeEn) || (((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
             -----------------------1----------------------    -------------------------------2-------------------------------
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT1,T2,T3

 LINE       209
 SUB-EXPRESSION ((tx_count == message_length_i) & MultimodeEn)
                 ---------------1--------------   -----2-----
-1--2-StatusTests
0-CoveredT1,T4,T5
1-CoveredT1,T2,T3

 LINE       209
 SUB-EXPRESSION (tx_count == message_length_i)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       227
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       233
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T6,T10

 LINE       239
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11CoveredT1,T2,T3

 LINE       331
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       331
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       333
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       344
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       344
 SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       354
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       354
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : prim_sha2_pad
Summary for FSM :: st_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 15 8 53.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StFifoReceive 190 Covered T1,T2,T3
StIdle 182 Covered T1,T2,T3
StLenHi 234 Covered T1,T2,T3
StLenLo 290 Covered T1,T2,T3
StPad00 240 Covered T1,T2,T3
StPad80 203 Covered T1,T2,T3


transitionsLine No.CoveredTests
StFifoReceive->StIdle 182 Covered T11,T12
StFifoReceive->StPad80 203 Covered T1,T2,T3
StIdle->StFifoReceive 190 Covered T1,T2,T3
StLenHi->StFifoReceive 317 Not Covered
StLenHi->StIdle 182 Not Covered
StLenHi->StLenLo 290 Covered T1,T2,T3
StLenLo->StFifoReceive 317 Not Covered
StLenLo->StIdle 182 Covered T1,T2,T3
StPad00->StFifoReceive 317 Not Covered
StPad00->StIdle 182 Not Covered
StPad00->StLenHi 278 Covered T1,T2,T3
StPad80->StFifoReceive 317 Not Covered
StPad80->StIdle 182 Not Covered
StPad80->StLenHi 234 Covered T1,T6,T10
StPad80->StPad00 240 Covered T1,T2,T3



Branch Coverage for Module : prim_sha2_pad
Line No.TotalCoveredPercent
Branches 71 59 83.10
TERNARY 57 3 3 100.00
TERNARY 63 3 3 100.00
TERNARY 344 3 3 100.00
IF 68 2 2 100.00
CASE 83 24 18 75.00
IF 141 1 1 100.00
IF 172 2 2 100.00
CASE 184 20 16 80.00
IF 316 3 3 100.00
IF 324 6 4 66.67
IF 340 2 2 100.00
IF 349 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -2-: 57 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 63 ((((~sha_en_i) || hash_go) || hash_done_i)) ? -2-: 63 (hash_process_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (hash_start_i) ? -2-: 344 (hash_done_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 83 case (sel_data) -2-: 94 if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) -3-: 95 case (message_length_i[4:3]) -4-: 102 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -5-: 103 case (message_length_i[5:3]) -6-: 123 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -7-: 123 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -8-: 130 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -9-: 130 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
FifoIn - - - - - - - - Covered T1,T2,T3
Pad80 1 2'b00 - - - - - - Covered T1,T2,T3
Pad80 1 2'b01 - - - - - - Covered T2,T4,T5
Pad80 1 2'b10 - - - - - - Covered T1,T2,T8
Pad80 1 2'b11 - - - - - - Covered T1,T3,T5
Pad80 1 default - - - - - - Not Covered
Pad80 0 - 1 3'b000 - - - - Covered T1,T2,T3
Pad80 0 - 1 3'b001 - - - - Covered T1,T2,T4
Pad80 0 - 1 3'b010 - - - - Covered T1,T2,T3
Pad80 0 - 1 3'b011 - - - - Covered T1,T2,T9
Pad80 0 - 1 3'b100 - - - - Covered T1,T2,T3
Pad80 0 - 1 3'b101 - - - - Covered T1,T2,T5
Pad80 0 - 1 3'b110 - - - - Covered T2,T3,T5
Pad80 0 - 1 3'b111 - - - - Covered T2,T3,T5
Pad80 0 - 1 default - - - - Not Covered
Pad80 0 - 0 - - - - - Not Covered
Pad00 - - - - - - - - Covered T1,T2,T3
LenHi - - - - 1 - - - Covered T1,T2,T3
LenHi - - - - 0 1 - - Covered T1,T2,T3
LenHi - - - - 0 0 - - Not Covered
LenLo - - - - - - 1 - Covered T1,T2,T3
LenLo - - - - - - 0 1 Covered T1,T2,T3
LenLo - - - - - - 0 0 Not Covered
default - - - - - - - - Not Covered


LineNo. Expression -1-: 141 if ((!MultimodeEn))

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


LineNo. Expression -1-: 172 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 184 case (st_q) -2-: 188 if ((sha_en_i && hash_go)) -3-: 198 if ((fifo_partial && fifo_rvalid_i)) -4-: 204 if ((!hash_process_flag_q)) -5-: 209 if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn)))) -6-: 227 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -7-: 227 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -8-: 233 if ((shaf_rready_i && txcnt_eq_1a0)) -9-: 239 if ((shaf_rready_i && (!txcnt_eq_1a0))) -10-: 276 if (shaf_rready_i) -11-: 278 if (txcnt_eq_1a0) -12-: 289 if (shaf_rready_i) -13-: 302 if (shaf_rready_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StFifoReceive - 1 - - - - - - - - - - Covered T1,T2,T3
StFifoReceive - 0 1 - - - - - - - - - Covered T1,T2,T3
StFifoReceive - 0 0 1 - - - - - - - - Covered T1,T2,T3
StFifoReceive - 0 0 0 - - - - - - - - Covered T1,T4,T5
StPad80 - - - - 1 - - - - - - - Covered T1,T2,T3
StPad80 - - - - 0 1 - - - - - - Covered T1,T2,T3
StPad80 - - - - 0 0 - - - - - - Not Covered
StPad80 - - - - - - 1 - - - - - Covered T1,T6,T10
StPad80 - - - - - - 0 1 - - - - Covered T1,T2,T3
StPad80 - - - - - - 0 0 - - - - Covered T1,T3,T4
StPad00 - - - - - - - - 1 1 - - Covered T1,T2,T3
StPad00 - - - - - - - - 1 0 - - Covered T1,T2,T3
StPad00 - - - - - - - - 0 - - - Covered T1,T5,T13
StLenHi - - - - - - - - - - 1 - Covered T1,T2,T3
StLenHi - - - - - - - - - - 0 - Not Covered
StLenLo - - - - - - - - - - - 1 Covered T1,T2,T3
StLenLo - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 316 if ((!sha_en_i)) -2-: 317 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 if (hash_start_i) -2-: 327 if (hash_continue_i) -3-: 330 if (inc_txcount) -4-: 331 if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) -5-: 333 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 1 - Covered T1,T2,T3
0 0 1 0 1 Covered T1,T2,T3
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 340 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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