Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6999552	1			T1	436		T2	33		T3	77389
all_values[1]	6999552	1			T1	436		T2	33		T3	77389
all_values[2]	6999552	1			T1	436		T2	33		T3	77389

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56526

1

T4

9

T5

14

T9

12

auto[1]

20942130

1

T1

1308

T2

99

T3

232167

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19088411

1

T1

1177

T2

95

T3

222256

auto[1]

1910245

1

T1

131

T2

4

T3

9911

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23079	1			T4	3		T18	177		T53	261
all_values[0]	auto[0]	auto[1]	162	1			T18	6		T53	2		T8	2
all_values[0]	auto[1]	auto[0]	6958537	1			T1	406		T2	29		T3	77195
all_values[0]	auto[1]	auto[1]	17774	1			T1	30		T2	4		T3	194
all_values[1]	auto[0]	auto[0]	15847	1			T4	3		T5	14		T9	12
all_values[1]	auto[0]	auto[1]	98	1			T8	1		T22	2		T19	1
all_values[1]	auto[1]	auto[0]	6983492	1			T1	436		T2	33		T3	77389
all_values[1]	auto[1]	auto[1]	115	1			T4	1		T8	7		T22	5
all_values[2]	auto[0]	auto[0]	7191	1			T4	1		T14	1		T8	3
all_values[2]	auto[0]	auto[1]	10149	1			T4	2		T14	2		T8	1
all_values[2]	auto[1]	auto[0]	5100265	1			T1	335		T2	33		T3	67672
all_values[2]	auto[1]	auto[1]	1881947	1			T1	101		T3	9717		T4	29159