ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Category 0 | 384 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Severity 0 | 384 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 384 | 100.00 |
Uncovered | 2 | 0.52 |
Success | 378 | 98.44 |
Failure | 0 | 0.00 |
Incomplete | 3 | 0.78 |
Without Attempts | 0 | 0.00 |
Excluded | 4 | 1.04 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_tlul_adapter.rvalidHighReqFifoEmpty | 0 | 0 | 206493108 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.rvalidHighWhenRspFifoFull | 0 | 0 | 206493108 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_packer.DataIStable_M | 0 | 0 | 206493108 | 562392 | 0 | 435 | |
tb.dut.u_packer.DataOStableWhenPending_A | 0 | 0 | 206493108 | 701781 | 0 | 435 | |
tb.dut.u_packer.FlushFollowedByDone_A | 0 | 0 | 206493108 | 16958 | 0 | 435 |
ASSERTIONS | CATEGORY | SEVERITY | EXCLUSION | EXCLUDE ANNOTATION | SRC |
tb.dut.u_tlul_adapter.u_rspfifo.DataKnown_A | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_sramreqfifo.DataKnown_A | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 215459709 | 200879 | 200879 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 215459709 | 493 | 493 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 215459709 | 501 | 501 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 215459709 | 312 | 312 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 215459709 | 44 | 44 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 215459709 | 238 | 238 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 215459709 | 337 | 337 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 215459709 | 11254 | 11254 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 215459709 | 1998204 | 1998204 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 215459709 | 20455091 | 20455091 | 579 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 215459709 | 200879 | 200879 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 215459709 | 493 | 493 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 215459709 | 501 | 501 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 215459709 | 312 | 312 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 215459709 | 44 | 44 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 215459709 | 238 | 238 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 215459709 | 337 | 337 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 215459709 | 11254 | 11254 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 215459709 | 1998204 | 1998204 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 215459709 | 20455091 | 20455091 | 579 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |