Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3599512

1

T1

161

T2

28

T3

37411

auto[1]

1072340

1

T1

142

T4

22946

T5

120

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086662

1

T1

208

T4

24303

T5

152

auto[1]

3585190

1

T1

95

T2

28

T3

37411

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2880804

1

T1

185

T3

37411

T4

45422

auto[1]

1791048

1

T1

118

T2

28

T4

33523

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3940507	1			T1	242		T2	24		T3	24926
fifo_depth[1]	139890	1			T1	12		T2	3		T3	2436
fifo_depth[2]	105140	1			T1	10		T2	1		T3	2398
fifo_depth[3]	79884	1			T1	9		T3	1913		T4	2452
fifo_depth[4]	64540	1			T1	6		T3	1362		T4	2011
fifo_depth[5]	54582	1			T1	6		T3	1177		T4	1827
fifo_depth[6]	51728	1			T1	6		T3	981		T4	1675
fifo_depth[7]	42186	1			T1	1		T3	778		T4	1425

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731345

1

T1

61

T2

4

T3

12485

auto[1]

3940507

1

T1

242

T2

24

T3

24926

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4668836

1

T1

303

T2

28

T3

37411

auto[1]

3016

1

T4

129

T7

1

T47

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

27576

1

T4

1794

T7

3

T14

6

auto[0]

auto[0]

auto[0]

auto[1]

20348

1

T4

248

T7

1

T14

4

auto[0]

auto[0]

auto[1]

auto[0]

410765

1

T3

12485

T4

14283

T6

2824

auto[0]

auto[0]

auto[1]

auto[1]

27385

1

T4

1756

T7

6

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

62576

1

T1

12

T4

1526

T5

3

auto[0]

auto[1]

auto[0]

auto[1]

60627

1

T1

12

T4

2693

T5

8

auto[0]

auto[1]

auto[1]

auto[0]

59815

1

T1

11

T2

4

T4

3139

auto[0]

auto[1]

auto[1]

auto[1]

62253

1

T1

26

T4

2151

T5

4

auto[1]

auto[0]

auto[0]

auto[0]

77217

1

T1

108

T4

597

T5

38

auto[1]

auto[0]

auto[0]

auto[1]

73123

1

T1

49

T4

1310

T5

47

auto[1]

auto[0]

auto[1]

auto[0]

2165723

1

T1

5

T3

24926

T4

25234

auto[1]

auto[0]

auto[1]

auto[1]

78667

1

T1

23

T4

200

T5

26

auto[1]

auto[1]

auto[0]

auto[0]

387207

1

T1

2

T4

5108

T5

33

auto[1]

auto[1]

auto[0]

auto[1]

377988

1

T1

25

T4

11027

T5

23

auto[1]

auto[1]

auto[1]

auto[0]

408633

1

T1

23

T2

24

T4

4318

auto[1]

auto[1]

auto[1]

auto[1]

371949

1

T1

7

T4

3561

T5

12

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

104435

1

T1

108

T4

2374

T5

38

auto[0]

auto[0]

auto[0]

auto[1]

93110

1

T1

49

T4

1558

T5

47

auto[0]

auto[0]

auto[1]

auto[0]

2575894

1

T1

5

T3

37411

T4

39517

auto[0]

auto[0]

auto[1]

auto[1]

105725

1

T1

23

T4

1901

T5

26

auto[0]

auto[1]

auto[0]

auto[0]

449682

1

T1

14

T4

6595

T5

36

auto[0]

auto[1]

auto[0]

auto[1]

438110

1

T1

37

T4

13707

T5

31

auto[0]

auto[1]

auto[1]

auto[0]

468211

1

T1

34

T2

28

T4

7454

auto[0]

auto[1]

auto[1]

auto[1]

433669

1

T1

33

T4

5710

T5

16

auto[1]

auto[0]

auto[0]

auto[0]

358

1

T4

17

T47

1

T115

1

auto[1]

auto[0]

auto[0]

auto[1]

361

1

T7

1

T115

1

T96

32

auto[1]

auto[0]

auto[1]

auto[0]

594

1

T116

12

T117

1

T96

4

auto[1]

auto[0]

auto[1]

auto[1]

327

1

T4

55

T116

34

T118

1

auto[1]

auto[1]

auto[0]

auto[0]

101

1

T4

39

T47

1

T33

2

auto[1]

auto[1]

auto[0]

auto[1]

505

1

T4

13

T33

1

T119

1

auto[1]

auto[1]

auto[1]

auto[0]

237

1

T4

3

T96

1

T119

1

auto[1]

auto[1]

auto[1]

auto[1]

533

1

T4

2

T96

6

T120

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	77217	1			T1	108		T4	597		T5	38
fifo_depth[0]	auto[0]	auto[0]	auto[1]	73123	1			T1	49		T4	1310		T5	47
fifo_depth[0]	auto[0]	auto[1]	auto[0]	2165723	1			T1	5		T3	24926		T4	25234
fifo_depth[0]	auto[0]	auto[1]	auto[1]	78667	1			T1	23		T4	200		T5	26
fifo_depth[0]	auto[1]	auto[0]	auto[0]	387207	1			T1	2		T4	5108		T5	33
fifo_depth[0]	auto[1]	auto[0]	auto[1]	377988	1			T1	25		T4	11027		T5	23
fifo_depth[0]	auto[1]	auto[1]	auto[0]	408633	1			T1	23		T2	24		T4	4318
fifo_depth[0]	auto[1]	auto[1]	auto[1]	371949	1			T1	7		T4	3561		T5	12
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1498	1			T4	16		T23	7		T53	107
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1372	1			T4	6		T53	7		T8	160
fifo_depth[1]	auto[0]	auto[1]	auto[0]	112067	1			T3	2436		T4	2519		T6	1613
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1653	1			T4	5		T53	50		T8	37
fifo_depth[1]	auto[1]	auto[0]	auto[0]	6519	1			T1	1		T4	50		T5	1
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5678	1			T1	4		T4	140		T5	5
fifo_depth[1]	auto[1]	auto[1]	auto[0]	5485	1			T1	3		T2	3		T4	38
fifo_depth[1]	auto[1]	auto[1]	auto[1]	5618	1			T1	4		T4	110		T5	3
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1450	1			T4	20		T23	5		T53	67
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1413	1			T4	5		T53	3		T8	131
fifo_depth[2]	auto[0]	auto[1]	auto[0]	77597	1			T3	2398		T4	2418		T6	749
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1645	1			T4	18		T53	36		T8	40
fifo_depth[2]	auto[1]	auto[0]	auto[0]	6332	1			T1	1		T4	46		T5	2
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5785	1			T1	1		T4	133		T5	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	5482	1			T1	3		T2	1		T4	44
fifo_depth[2]	auto[1]	auto[1]	auto[1]	5436	1			T1	5		T4	145		T5	1
fifo_depth[3]	auto[0]	auto[0]	auto[0]	975	1			T4	17		T23	1		T53	21
fifo_depth[3]	auto[0]	auto[0]	auto[1]	901	1			T4	6		T8	150		T64	4
fifo_depth[3]	auto[0]	auto[1]	auto[0]	55274	1			T3	1913		T4	2066		T6	320
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1096	1			T4	9		T53	13		T8	37
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5974	1			T1	2		T4	52		T18	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	5432	1			T1	2		T4	125		T5	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	5053	1			T1	1		T4	38		T5	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	5179	1			T1	4		T4	139		T18	2
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1611	1			T4	19		T53	7		T8	31
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1156	1			T4	6		T8	154		T64	2
fifo_depth[4]	auto[0]	auto[1]	auto[0]	38915	1			T3	1362		T4	1523		T6	106
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1228	1			T4	55		T53	4		T8	38
fifo_depth[4]	auto[1]	auto[0]	auto[0]	6015	1			T1	1		T4	51		T18	3
fifo_depth[4]	auto[1]	auto[0]	auto[1]	5346	1			T1	1		T4	114		T18	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5056	1			T1	1		T4	41		T41	3
fifo_depth[4]	auto[1]	auto[1]	auto[1]	5213	1			T1	3		T4	202		T18	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1001	1			T4	23		T53	6		T8	32
fifo_depth[5]	auto[0]	auto[0]	auto[1]	715	1			T4	5		T8	143		T64	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	30982	1			T3	1177		T4	1348		T6	25
fifo_depth[5]	auto[0]	auto[1]	auto[1]	952	1			T4	47		T8	37		T64	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	5824	1			T1	2		T4	64		T18	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	5153	1			T1	2		T4	140		T5	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	4953	1			T1	1		T4	42		T41	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	5002	1			T1	1		T4	158		T18	4
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1561	1			T4	49		T53	1		T8	26
fifo_depth[6]	auto[0]	auto[0]	auto[1]	890	1			T4	6		T8	132		T64	2
fifo_depth[6]	auto[0]	auto[1]	auto[0]	26787	1			T3	981		T4	1156		T6	7
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1359	1			T4	26		T8	31		T64	1
fifo_depth[6]	auto[1]	auto[0]	auto[0]	5693	1			T1	2		T4	48		T18	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	5285	1			T1	1		T4	198		T18	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5041	1			T1	1		T4	46		T18	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	5112	1			T1	2		T4	146		T54	385
fifo_depth[7]	auto[0]	auto[0]	auto[0]	955	1			T4	19		T8	19		T67	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	596	1			T4	5		T8	120		T64	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	20787	1			T3	778		T4	953		T6	4
fifo_depth[7]	auto[0]	auto[1]	auto[1]	862	1			T4	44		T8	32		T121	33
fifo_depth[7]	auto[1]	auto[0]	auto[0]	5203	1			T1	1		T4	46		T54	108
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4709	1			T4	123		T54	88		T8	189
fifo_depth[7]	auto[1]	auto[1]	auto[0]	4400	1			T4	36		T41	4		T54	91
fifo_depth[7]	auto[1]	auto[1]	auto[1]	4674	1			T4	199		T54	346		T8	241