Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6999552	1			T1	436		T2	33		T3	77389
all_pins[1]	6999552	1			T1	436		T2	33		T3	77389
all_pins[2]	6999552	1			T1	436		T2	33		T3	77389

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19098599	1			T1	1177		T2	95		T3	222256
values[0x1]	1900057	1			T1	131		T2	4		T3	9911
transitions[0x0=>0x1]	1899986	1			T1	131		T2	4		T3	9911
transitions[0x1=>0x0]	1899993	1			T1	131		T2	4		T3	9911

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6981560	1			T1	406		T2	29		T3	77195
all_pins[0]	values[0x1]	17992	1			T1	30		T2	4		T3	194
all_pins[0]	transitions[0x0=>0x1]	17960	1			T1	30		T2	4		T3	194
all_pins[0]	transitions[0x1=>0x0]	1881922	1			T1	101		T3	9717		T4	29159
all_pins[1]	values[0x0]	6999434	1			T1	436		T2	33		T3	77389
all_pins[1]	values[0x1]	118	1			T4	1		T8	7		T22	5
all_pins[1]	transitions[0x0=>0x1]	104	1			T4	1		T8	7		T22	4
all_pins[1]	transitions[0x1=>0x0]	17978	1			T1	30		T2	4		T3	194
all_pins[2]	values[0x0]	5117605	1			T1	335		T2	33		T3	67672
all_pins[2]	values[0x1]	1881947	1			T1	101		T3	9717		T4	29159
all_pins[2]	transitions[0x0=>0x1]	1881922	1			T1	101		T3	9717		T4	29159
all_pins[2]	transitions[0x1=>0x0]	93	1			T4	1		T8	7		T22	4