Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 448 1 T8 7 T22 14 T19 7
all_values[1] 448 1 T8 7 T22 14 T19 7
all_values[2] 448 1 T8 7 T22 14 T19 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 715 1 T8 5 T22 14 T19 11
auto[1] 629 1 T8 16 T22 28 T19 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 488 1 T8 7 T22 18 T19 9
auto[1] 856 1 T8 14 T22 24 T19 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 776 1 T8 13 T22 26 T19 15
auto[1] 568 1 T8 8 T22 16 T19 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 77 1 T8 1 T22 4 T68 3
all_values[0] auto[0] auto[0] auto[1] 55 1 T22 2 T19 1 T68 2
all_values[0] auto[0] auto[1] auto[0] 97 1 T22 2 T19 2 T68 3
all_values[0] auto[0] auto[1] auto[1] 43 1 T8 3 T22 2 T19 2
all_values[0] auto[1] auto[0] auto[1] 100 1 T8 1 T19 2 T68 5
all_values[0] auto[1] auto[1] auto[1] 76 1 T8 2 T22 4 T69 1
all_values[1] auto[0] auto[0] auto[0] 70 1 T22 1 T19 3 T68 2
all_values[1] auto[0] auto[0] auto[1] 47 1 T22 1 T19 1 T68 1
all_values[1] auto[0] auto[1] auto[0] 75 1 T8 1 T22 2 T19 2
all_values[1] auto[0] auto[1] auto[1] 60 1 T8 3 T22 3 T68 3
all_values[1] auto[1] auto[0] auto[1] 108 1 T19 1 T68 5 T69 3
all_values[1] auto[1] auto[1] auto[1] 88 1 T8 3 T22 7 T68 3
all_values[2] auto[0] auto[0] auto[0] 107 1 T8 3 T22 5 T19 1
all_values[2] auto[0] auto[0] auto[1] 46 1 T19 2 T68 3 T69 2
all_values[2] auto[0] auto[1] auto[0] 62 1 T8 2 T22 4 T19 1
all_values[2] auto[0] auto[1] auto[1] 37 1 T68 3 T69 2 T20 1
all_values[2] auto[1] auto[0] auto[1] 105 1 T22 1 T68 6 T69 3
all_values[2] auto[1] auto[1] auto[1] 91 1 T8 2 T22 4 T19 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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