Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	1343	1			T1	10		T4	21		T5	9
sha2_384	1363	1			T1	8		T4	19		T5	5
sha2_256	14252	1			T1	7		T2	4		T3	194

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15075

1

T1

13

T2

4

T3

194

auto[1]

1883

1

T1

12

T4

29

T5

10

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1984

1

T1

18

T4

32

T5

12

auto[1]

14974

1

T1

7

T2

4

T3

194

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2152

1

T1

10

T2

4

T4

40

disabled

14806

1

T1

15

T3

194

T4

222

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	635	1			T1	5		T4	6		T5	5
key_1024	557	1			T1	1		T4	7		T5	4
key_512	646	1			T1	7		T4	12		T5	1
key_384	673	1			T1	6		T4	9		T5	1
key_256	13746	1			T1	2		T2	4		T3	194
key_128	701	1			T1	4		T4	15		T5	4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16958

1

T1

25

T2

4

T3

194

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	497	1			T1	3		T4	9		T5	1
enabled	auto[0]	auto[1]	472	1			T1	3		T4	11		T5	3
enabled	auto[1]	auto[0]	717	1			T1	1		T2	4		T4	14
enabled	auto[1]	auto[1]	466	1			T1	3		T4	6		T5	1
disabled	auto[0]	auto[0]	546	1			T1	8		T4	9		T5	4
disabled	auto[0]	auto[1]	469	1			T1	4		T4	3		T5	4
disabled	auto[1]	auto[0]	13315	1			T1	1		T3	194		T4	201
disabled	auto[1]	auto[1]	476	1			T1	2		T4	9		T5	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2152

1

T1

10

T2

4

T4

40

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14806

1

T1

15

T3

194

T4

222

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	221	1			T1	2		T4	3		T5	2
key_none	sha2_384	207	1			T1	2		T4	1		T5	1
key_none	sha2_256	207	1			T1	1		T4	2		T5	2
key_1024	sha2_512	237	1			T1	1		T4	3		T5	1
key_1024	sha2_384	234	1			T4	4		T5	2		T7	2
key_512	sha2_512	227	1			T1	4		T4	3		T9	1
key_512	sha2_384	218	1			T4	4		T5	1		T7	2
key_512	sha2_256	201	1			T1	3		T4	5		T7	2
key_384	sha2_512	211	1			T1	1		T4	3		T5	1
key_384	sha2_384	229	1			T1	4		T4	3		T9	2
key_384	sha2_256	233	1			T1	1		T4	3		T14	1
key_256	sha2_512	213	1			T4	4		T5	2		T9	1
key_256	sha2_384	228	1			T1	1		T4	3		T7	2
key_256	sha2_256	13305	1			T1	1		T2	4		T3	194
key_128	sha2_512	234	1			T1	2		T4	5		T5	3
key_128	sha2_384	247	1			T1	1		T4	4		T5	1
key_128	sha2_256	220	1			T1	1		T4	6		T7	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

86

1

T5

1

T9

2

T18

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	221	1			T1	2		T4	3		T5	2
key_none	sha2_384	207	1			T1	2		T4	1		T5	1
key_none	sha2_256	207	1			T1	1		T4	2		T5	2
key_1024	sha2_512	237	1			T1	1		T4	3		T5	1
key_1024	sha2_384	234	1			T4	4		T5	2		T7	2
key_1024	sha2_256	86	1			T5	1		T9	2		T18	1
key_512	sha2_512	227	1			T1	4		T4	3		T9	1
key_512	sha2_384	218	1			T4	4		T5	1		T7	2
key_512	sha2_256	201	1			T1	3		T4	5		T7	2
key_384	sha2_512	211	1			T1	1		T4	3		T5	1
key_384	sha2_384	229	1			T1	4		T4	3		T9	2
key_384	sha2_256	233	1			T1	1		T4	3		T14	1
key_256	sha2_512	213	1			T4	4		T5	2		T9	1
key_256	sha2_384	228	1			T1	1		T4	3		T7	2
key_256	sha2_256	13305	1			T1	1		T2	4		T3	194
key_128	sha2_512	234	1			T1	2		T4	5		T5	3
key_128	sha2_384	247	1			T1	1		T4	4		T5	1
key_128	sha2_256	220	1			T1	1		T4	6		T7	2