Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.35 95.76 93.95 100.00 73.68 91.67 99.49 70.90


Total test records in report: 600
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T515 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.26684199 May 12 01:29:41 PM PDT 24 May 12 01:29:43 PM PDT 24 50143174 ps
T516 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.74550312 May 12 01:29:59 PM PDT 24 May 12 01:30:02 PM PDT 24 345244435 ps
T517 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.542711676 May 12 01:29:58 PM PDT 24 May 12 01:30:00 PM PDT 24 37213382 ps
T518 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2255382937 May 12 01:30:19 PM PDT 24 May 12 01:30:22 PM PDT 24 171002222 ps
T114 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3104705619 May 12 01:30:02 PM PDT 24 May 12 01:30:04 PM PDT 24 180714829 ps
T519 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3455246871 May 12 01:30:22 PM PDT 24 May 12 01:30:25 PM PDT 24 32944901 ps
T520 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1140489196 May 12 01:30:21 PM PDT 24 May 12 01:30:23 PM PDT 24 12491038 ps
T521 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.495496070 May 12 01:29:48 PM PDT 24 May 12 01:30:04 PM PDT 24 12423876088 ps
T522 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3579871327 May 12 01:30:18 PM PDT 24 May 12 01:30:21 PM PDT 24 94284435 ps
T86 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4251855561 May 12 01:30:04 PM PDT 24 May 12 01:30:05 PM PDT 24 122691390 ps
T523 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3158323933 May 12 01:29:49 PM PDT 24 May 12 01:29:51 PM PDT 24 36973568 ps
T524 /workspace/coverage/cover_reg_top/39.hmac_intr_test.682980587 May 12 01:30:24 PM PDT 24 May 12 01:30:25 PM PDT 24 40903058 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2518746608 May 12 01:29:36 PM PDT 24 May 12 01:29:39 PM PDT 24 345905472 ps
T525 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.697087322 May 12 01:29:56 PM PDT 24 May 12 01:29:59 PM PDT 24 320250925 ps
T526 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1398912496 May 12 01:30:20 PM PDT 24 May 12 01:30:26 PM PDT 24 127145651 ps
T527 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2971379888 May 12 01:30:02 PM PDT 24 May 12 01:30:03 PM PDT 24 57327570 ps
T528 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1506243537 May 12 01:30:20 PM PDT 24 May 12 01:30:23 PM PDT 24 18327427 ps
T529 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1280543135 May 12 01:29:44 PM PDT 24 May 12 01:29:46 PM PDT 24 19425641 ps
T530 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4227451569 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 14828857 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2759957713 May 12 01:29:36 PM PDT 24 May 12 01:29:37 PM PDT 24 30330206 ps
T531 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.698806211 May 12 01:30:20 PM PDT 24 May 12 01:30:24 PM PDT 24 357119574 ps
T532 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2039302257 May 12 01:29:40 PM PDT 24 May 12 01:42:30 PM PDT 24 208705927887 ps
T533 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1071440525 May 12 01:29:57 PM PDT 24 May 12 01:29:59 PM PDT 24 156579475 ps
T534 /workspace/coverage/cover_reg_top/17.hmac_intr_test.888185435 May 12 01:30:17 PM PDT 24 May 12 01:30:19 PM PDT 24 48117037 ps
T535 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2945060549 May 12 01:30:20 PM PDT 24 May 12 01:30:24 PM PDT 24 442776508 ps
T536 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1047590016 May 12 01:30:24 PM PDT 24 May 12 01:30:25 PM PDT 24 26355313 ps
T537 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2119154788 May 12 01:30:17 PM PDT 24 May 12 01:30:19 PM PDT 24 66571620 ps
T538 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.522910351 May 12 01:30:19 PM PDT 24 May 12 01:30:22 PM PDT 24 29825926 ps
T539 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2708192180 May 12 01:30:23 PM PDT 24 May 12 01:30:25 PM PDT 24 14785275 ps
T540 /workspace/coverage/cover_reg_top/1.hmac_intr_test.575380675 May 12 01:29:41 PM PDT 24 May 12 01:29:42 PM PDT 24 14293392 ps
T87 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2019886883 May 12 01:29:57 PM PDT 24 May 12 01:30:00 PM PDT 24 637279762 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4114029925 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 53994234 ps
T542 /workspace/coverage/cover_reg_top/2.hmac_intr_test.410989832 May 12 01:29:57 PM PDT 24 May 12 01:29:58 PM PDT 24 56212204 ps
T543 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.45427617 May 12 01:30:19 PM PDT 24 May 12 01:30:22 PM PDT 24 79209302 ps
T544 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1664085958 May 12 01:30:04 PM PDT 24 May 12 01:30:05 PM PDT 24 35305604 ps
T89 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3113072972 May 12 01:30:18 PM PDT 24 May 12 01:30:20 PM PDT 24 53748760 ps
T545 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4256830924 May 12 01:30:02 PM PDT 24 May 12 01:30:03 PM PDT 24 22204064 ps
T546 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1989003368 May 12 01:30:17 PM PDT 24 May 12 01:30:19 PM PDT 24 83499248 ps
T547 /workspace/coverage/cover_reg_top/28.hmac_intr_test.106707031 May 12 01:30:18 PM PDT 24 May 12 01:30:20 PM PDT 24 58285414 ps
T548 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1925321260 May 12 01:29:56 PM PDT 24 May 12 01:29:59 PM PDT 24 249408909 ps
T549 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3622566474 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 19092272 ps
T550 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3193873513 May 12 01:30:07 PM PDT 24 May 12 01:30:08 PM PDT 24 61705740 ps
T551 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1637340492 May 12 01:29:57 PM PDT 24 May 12 01:29:59 PM PDT 24 179392816 ps
T552 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.420417780 May 12 01:30:19 PM PDT 24 May 12 01:37:13 PM PDT 24 97569490729 ps
T553 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1721957866 May 12 01:30:23 PM PDT 24 May 12 01:30:25 PM PDT 24 33641808 ps
T554 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4186504853 May 12 01:30:09 PM PDT 24 May 12 01:30:10 PM PDT 24 72543831 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.272509890 May 12 01:29:41 PM PDT 24 May 12 01:29:42 PM PDT 24 53931905 ps
T555 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4101425353 May 12 01:30:04 PM PDT 24 May 12 01:30:06 PM PDT 24 101557250 ps
T556 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1878210342 May 12 01:30:19 PM PDT 24 May 12 01:30:24 PM PDT 24 288572984 ps
T111 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1788712208 May 12 01:30:06 PM PDT 24 May 12 01:30:09 PM PDT 24 353368004 ps
T557 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.118343089 May 12 01:29:45 PM PDT 24 May 12 01:29:46 PM PDT 24 23876100 ps
T558 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2627495977 May 12 01:29:48 PM PDT 24 May 12 01:29:52 PM PDT 24 216893433 ps
T559 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2611362181 May 12 01:30:07 PM PDT 24 May 12 01:30:09 PM PDT 24 310041046 ps
T560 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.948954948 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 93953491 ps
T561 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1296155387 May 12 01:30:03 PM PDT 24 May 12 01:30:07 PM PDT 24 279727366 ps
T562 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3092790618 May 12 01:30:17 PM PDT 24 May 12 01:30:21 PM PDT 24 79703009 ps
T563 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1898414723 May 12 01:30:23 PM PDT 24 May 12 01:30:25 PM PDT 24 24503896 ps
T564 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1527226025 May 12 01:30:19 PM PDT 24 May 12 01:30:23 PM PDT 24 83983717 ps
T565 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3752038520 May 12 01:30:10 PM PDT 24 May 12 01:30:11 PM PDT 24 46754308 ps
T566 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1886516323 May 12 01:30:17 PM PDT 24 May 12 01:30:20 PM PDT 24 123973370 ps
T567 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1598314248 May 12 01:29:52 PM PDT 24 May 12 01:29:53 PM PDT 24 54155863 ps
T568 /workspace/coverage/cover_reg_top/49.hmac_intr_test.380900377 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 47965590 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2432297434 May 12 01:29:51 PM PDT 24 May 12 01:29:55 PM PDT 24 228910144 ps
T569 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2687171131 May 12 01:30:18 PM PDT 24 May 12 01:30:20 PM PDT 24 26134685 ps
T570 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2318475379 May 12 01:30:07 PM PDT 24 May 12 01:30:09 PM PDT 24 33769110 ps
T571 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3129072894 May 12 01:30:19 PM PDT 24 May 12 01:30:22 PM PDT 24 148172411 ps
T572 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1736156139 May 12 01:30:18 PM PDT 24 May 12 01:30:20 PM PDT 24 29586235 ps
T573 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.943813434 May 12 01:29:50 PM PDT 24 May 12 01:29:52 PM PDT 24 100497859 ps
T574 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3093593852 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 15285759 ps
T575 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3831420887 May 12 01:30:17 PM PDT 24 May 12 01:30:18 PM PDT 24 36095767 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1190749280 May 12 01:29:41 PM PDT 24 May 12 01:29:47 PM PDT 24 1515392526 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3132436576 May 12 01:29:36 PM PDT 24 May 12 01:29:39 PM PDT 24 163534016 ps
T577 /workspace/coverage/cover_reg_top/29.hmac_intr_test.383358385 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 12281470 ps
T578 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.533965678 May 12 01:30:04 PM PDT 24 May 12 01:30:08 PM PDT 24 225812375 ps
T579 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3910003063 May 12 01:29:55 PM PDT 24 May 12 01:29:56 PM PDT 24 52148804 ps
T580 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1714480620 May 12 01:30:18 PM PDT 24 May 12 01:30:20 PM PDT 24 22999099 ps
T581 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2279244211 May 12 01:29:55 PM PDT 24 May 12 01:29:59 PM PDT 24 177887745 ps
T582 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3190969656 May 12 01:30:21 PM PDT 24 May 12 01:30:24 PM PDT 24 94681436 ps
T583 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2187213448 May 12 01:29:35 PM PDT 24 May 12 01:29:37 PM PDT 24 46801225 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.17240372 May 12 01:29:50 PM PDT 24 May 12 01:30:07 PM PDT 24 1055845670 ps
T584 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1497848205 May 12 01:30:20 PM PDT 24 May 12 01:30:24 PM PDT 24 219392805 ps
T585 /workspace/coverage/cover_reg_top/10.hmac_intr_test.40999163 May 12 01:30:08 PM PDT 24 May 12 01:30:09 PM PDT 24 33031778 ps
T110 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1299931367 May 12 01:30:19 PM PDT 24 May 12 01:30:24 PM PDT 24 220619172 ps
T93 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.569082755 May 12 01:30:20 PM PDT 24 May 12 01:30:23 PM PDT 24 65691992 ps
T586 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.253420910 May 12 01:30:20 PM PDT 24 May 12 01:30:24 PM PDT 24 37453796 ps
T587 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3379362536 May 12 01:30:03 PM PDT 24 May 12 01:30:05 PM PDT 24 155836599 ps
T588 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4231087374 May 12 01:29:47 PM PDT 24 May 12 01:29:49 PM PDT 24 31987566 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1575330153 May 12 01:29:48 PM PDT 24 May 12 01:29:49 PM PDT 24 45062214 ps
T589 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3617970174 May 12 01:30:20 PM PDT 24 May 12 01:30:23 PM PDT 24 89083422 ps
T590 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1715804130 May 12 01:29:36 PM PDT 24 May 12 01:29:40 PM PDT 24 134836294 ps
T591 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1785963354 May 12 01:30:22 PM PDT 24 May 12 01:30:24 PM PDT 24 20675756 ps
T592 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3815745455 May 12 01:30:25 PM PDT 24 May 12 01:30:26 PM PDT 24 13189032 ps
T593 /workspace/coverage/cover_reg_top/26.hmac_intr_test.581637211 May 12 01:30:23 PM PDT 24 May 12 01:30:25 PM PDT 24 15199202 ps
T594 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2928184621 May 12 01:30:20 PM PDT 24 May 12 01:30:23 PM PDT 24 482246221 ps
T595 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1913193598 May 12 01:30:07 PM PDT 24 May 12 01:30:10 PM PDT 24 183914596 ps
T596 /workspace/coverage/cover_reg_top/23.hmac_intr_test.675354165 May 12 01:30:17 PM PDT 24 May 12 01:30:19 PM PDT 24 58480043 ps
T597 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4238107754 May 12 01:30:23 PM PDT 24 May 12 01:30:25 PM PDT 24 23353274 ps
T598 /workspace/coverage/cover_reg_top/12.hmac_intr_test.441055935 May 12 01:30:19 PM PDT 24 May 12 01:30:20 PM PDT 24 29928640 ps
T599 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2874440207 May 12 01:30:25 PM PDT 24 May 12 01:30:26 PM PDT 24 14538668 ps
T600 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1764078133 May 12 01:30:06 PM PDT 24 May 12 01:30:08 PM PDT 24 86719383 ps

Test location /workspace/coverage/default/1.hmac_stress_all.3937648395
Short name T4
Test name
Test status
Simulation time 52438758119 ps
CPU time 1251.27 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:54:22 PM PDT 24
Peak memory 701252 kb
Host smart-e7e72832-1c21-49b4-992d-0d08c751c29f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937648395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3937648395
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3297170535
Short name T8
Test name
Test status
Simulation time 198365360998 ps
CPU time 3806.19 seconds
Started May 12 01:33:37 PM PDT 24
Finished May 12 02:37:05 PM PDT 24
Peak memory 859136 kb
Host smart-d2936e44-35fa-4f9b-9d04-08e05e279196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297170535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3297170535
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2255652253
Short name T15
Test name
Test status
Simulation time 26479521 ps
CPU time 0.61 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:33:50 PM PDT 24
Peak memory 197044 kb
Host smart-931e53e1-697d-45dd-b641-d68e3c9a20e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255652253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2255652253
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.966129887
Short name T31
Test name
Test status
Simulation time 184359296 ps
CPU time 0.95 seconds
Started May 12 01:33:28 PM PDT 24
Finished May 12 01:33:30 PM PDT 24
Peak memory 219840 kb
Host smart-6a173442-020c-4783-9db3-3b850a60885d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966129887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.966129887
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.280355659
Short name T51
Test name
Test status
Simulation time 85579412 ps
CPU time 1.8 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 200084 kb
Host smart-34fc3d17-b776-4f72-937f-07c7a9627cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280355659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.280355659
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1115578616
Short name T68
Test name
Test status
Simulation time 292620042620 ps
CPU time 2114.96 seconds
Started May 12 01:34:52 PM PDT 24
Finished May 12 02:10:08 PM PDT 24
Peak memory 225312 kb
Host smart-0ec96cc3-032b-4627-aad4-246e0b44dafc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115578616 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1115578616
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.173225151
Short name T84
Test name
Test status
Simulation time 1141832990 ps
CPU time 14.5 seconds
Started May 12 01:29:37 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 199976 kb
Host smart-bb8596ae-1ad5-463a-a719-df4573db151a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173225151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.173225151
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1595639465
Short name T23
Test name
Test status
Simulation time 712432669 ps
CPU time 3.36 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:15 PM PDT 24
Peak memory 200616 kb
Host smart-9b77a12c-be3e-4bd5-be5a-f19ccabcd4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595639465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1595639465
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2456644205
Short name T106
Test name
Test status
Simulation time 197747203 ps
CPU time 3.02 seconds
Started May 12 01:29:35 PM PDT 24
Finished May 12 01:29:38 PM PDT 24
Peak memory 199996 kb
Host smart-410a729d-3674-4e35-ae61-f6245a63b953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456644205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2456644205
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/30.hmac_stress_all.613600385
Short name T98
Test name
Test status
Simulation time 2827716650 ps
CPU time 519.96 seconds
Started May 12 01:34:30 PM PDT 24
Finished May 12 01:43:10 PM PDT 24
Peak memory 713164 kb
Host smart-943e7329-6ad3-45d8-b2bd-ff25a7b82e82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613600385 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.613600385
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2088618593
Short name T105
Test name
Test status
Simulation time 270001120 ps
CPU time 3.04 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 200136 kb
Host smart-402a0bce-6af1-4386-87e8-5948e5f49616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088618593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2088618593
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_error.2935092891
Short name T10
Test name
Test status
Simulation time 18688730448 ps
CPU time 131.27 seconds
Started May 12 01:33:54 PM PDT 24
Finished May 12 01:36:06 PM PDT 24
Peak memory 200704 kb
Host smart-bc7428d8-06ab-4e80-b372-6a89f53a60b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935092891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2935092891
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1551030942
Short name T101
Test name
Test status
Simulation time 2825997759 ps
CPU time 318.56 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:39:24 PM PDT 24
Peak memory 458420 kb
Host smart-aaabf886-d236-4f83-83cb-43a0c0cfa9b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551030942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1551030942
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2351421157
Short name T103
Test name
Test status
Simulation time 17121911048 ps
CPU time 1061.33 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:52:33 PM PDT 24
Peak memory 744088 kb
Host smart-cb52cbd8-473a-4b82-8cf6-dc657b1d3f9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351421157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2351421157
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1788712208
Short name T111
Test name
Test status
Simulation time 353368004 ps
CPU time 3.29 seconds
Started May 12 01:30:06 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 200028 kb
Host smart-94b158e3-aa9d-4545-b0a3-92741a361bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788712208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1788712208
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2405407420
Short name T96
Test name
Test status
Simulation time 944520502 ps
CPU time 48.56 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:34:39 PM PDT 24
Peak memory 200532 kb
Host smart-88ebb905-e386-410e-94e5-785f1fb48df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405407420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2405407420
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3943344906
Short name T99
Test name
Test status
Simulation time 10618352397 ps
CPU time 101.12 seconds
Started May 12 01:34:16 PM PDT 24
Finished May 12 01:35:57 PM PDT 24
Peak memory 200696 kb
Host smart-4e1020cb-2171-4f43-8f8c-04b3482da01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943344906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3943344906
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.553675685
Short name T85
Test name
Test status
Simulation time 444240885 ps
CPU time 8.85 seconds
Started May 12 01:29:35 PM PDT 24
Finished May 12 01:29:45 PM PDT 24
Peak memory 200084 kb
Host smart-b3a3372e-d1e8-44f4-952e-3a118baa5a77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553675685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.553675685
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.978722638
Short name T499
Test name
Test status
Simulation time 39146186 ps
CPU time 0.72 seconds
Started May 12 01:29:35 PM PDT 24
Finished May 12 01:29:36 PM PDT 24
Peak memory 197856 kb
Host smart-d9512b9d-2a35-4e6a-b6a9-33ebab2a46b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978722638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.978722638
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.375184416
Short name T76
Test name
Test status
Simulation time 398776797 ps
CPU time 2.53 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200140 kb
Host smart-ec513481-ba30-4da2-86fb-101a70dc9663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375184416 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.375184416
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2759957713
Short name T88
Test name
Test status
Simulation time 30330206 ps
CPU time 0.79 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:29:37 PM PDT 24
Peak memory 199616 kb
Host smart-fff0996a-94c9-4424-978e-25dbd786f2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759957713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2759957713
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2187213448
Short name T583
Test name
Test status
Simulation time 46801225 ps
CPU time 0.59 seconds
Started May 12 01:29:35 PM PDT 24
Finished May 12 01:29:37 PM PDT 24
Peak memory 194868 kb
Host smart-9e3a19db-6af5-4300-be96-fc6ac697ae6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187213448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2187213448
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2836684266
Short name T513
Test name
Test status
Simulation time 59127597 ps
CPU time 1.16 seconds
Started May 12 01:29:37 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 199900 kb
Host smart-79c05f4e-3572-4864-a637-48dd66471d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836684266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2836684266
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1715804130
Short name T590
Test name
Test status
Simulation time 134836294 ps
CPU time 3.6 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:29:40 PM PDT 24
Peak memory 200060 kb
Host smart-cc0d1c43-a355-48d9-ab54-92c1ca6bd68d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715804130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1715804130
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1190749280
Short name T91
Test name
Test status
Simulation time 1515392526 ps
CPU time 6.19 seconds
Started May 12 01:29:41 PM PDT 24
Finished May 12 01:29:47 PM PDT 24
Peak memory 199968 kb
Host smart-f1434d31-861a-4ca3-8663-099ed04b70a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190749280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1190749280
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3657105240
Short name T511
Test name
Test status
Simulation time 639715487 ps
CPU time 13.85 seconds
Started May 12 01:29:40 PM PDT 24
Finished May 12 01:29:55 PM PDT 24
Peak memory 199068 kb
Host smart-d6bf8279-bf9d-4920-8935-1f184a50f6ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657105240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3657105240
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3900162950
Short name T81
Test name
Test status
Simulation time 31781267 ps
CPU time 0.84 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:46 PM PDT 24
Peak memory 199060 kb
Host smart-f8e154e2-8c5d-4fb9-ab33-ca5712642b43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900162950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3900162950
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2039302257
Short name T532
Test name
Test status
Simulation time 208705927887 ps
CPU time 769.73 seconds
Started May 12 01:29:40 PM PDT 24
Finished May 12 01:42:30 PM PDT 24
Peak memory 224824 kb
Host smart-4e2d0536-e34c-473d-9021-67b8e35504bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039302257 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2039302257
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.272509890
Short name T90
Test name
Test status
Simulation time 53931905 ps
CPU time 0.95 seconds
Started May 12 01:29:41 PM PDT 24
Finished May 12 01:29:42 PM PDT 24
Peak memory 199332 kb
Host smart-82224a4f-b9f5-4c33-9246-ca6c1c01e29b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272509890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.272509890
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.575380675
Short name T540
Test name
Test status
Simulation time 14293392 ps
CPU time 0.6 seconds
Started May 12 01:29:41 PM PDT 24
Finished May 12 01:29:42 PM PDT 24
Peak memory 194820 kb
Host smart-e8db3130-e783-409e-89cf-fa89ec193146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575380675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.575380675
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.26684199
Short name T515
Test name
Test status
Simulation time 50143174 ps
CPU time 1.16 seconds
Started May 12 01:29:41 PM PDT 24
Finished May 12 01:29:43 PM PDT 24
Peak memory 200108 kb
Host smart-07d9a0c7-3667-4957-8ba9-2546de4a272f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_o
utstanding.26684199
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3132436576
Short name T576
Test name
Test status
Simulation time 163534016 ps
CPU time 2.99 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200040 kb
Host smart-bdc48b9b-e11f-4afa-b81c-3b2275a95e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132436576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3132436576
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2518746608
Short name T107
Test name
Test status
Simulation time 345905472 ps
CPU time 2.82 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200080 kb
Host smart-e6367eae-eb53-4a1f-87b5-cde63b24acf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518746608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2518746608
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2750394172
Short name T500
Test name
Test status
Simulation time 46341735 ps
CPU time 3.05 seconds
Started May 12 01:30:06 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 200144 kb
Host smart-edd1e507-baf6-4419-b696-162c021acfa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750394172 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2750394172
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3193873513
Short name T550
Test name
Test status
Simulation time 61705740 ps
CPU time 0.69 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 197856 kb
Host smart-d9d13a11-258c-46f9-b413-13194611ed5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193873513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3193873513
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.40999163
Short name T585
Test name
Test status
Simulation time 33031778 ps
CPU time 0.59 seconds
Started May 12 01:30:08 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 194908 kb
Host smart-7788e7cd-c27d-4ae0-9e0f-33ba4cc0cde7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40999163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.40999163
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4186504853
Short name T554
Test name
Test status
Simulation time 72543831 ps
CPU time 1.07 seconds
Started May 12 01:30:09 PM PDT 24
Finished May 12 01:30:10 PM PDT 24
Peak memory 199956 kb
Host smart-7f10843a-761d-47a5-a0ad-7fb2e6ff1d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186504853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4186504853
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2611362181
Short name T559
Test name
Test status
Simulation time 310041046 ps
CPU time 1.6 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 200028 kb
Host smart-4e258b9a-e70c-4035-8488-4bc074a1e44b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611362181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2611362181
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.522910351
Short name T538
Test name
Test status
Simulation time 29825926 ps
CPU time 1.77 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 200104 kb
Host smart-2e4909d0-0a65-421f-a0be-930c1729a46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522910351 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.522910351
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2834581324
Short name T497
Test name
Test status
Simulation time 41603594 ps
CPU time 0.72 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 198120 kb
Host smart-1c7f864f-c4bf-4e2d-839d-514fc4a93bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834581324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2834581324
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2224286471
Short name T506
Test name
Test status
Simulation time 35883943 ps
CPU time 0.57 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 194888 kb
Host smart-9ac35f11-a0ed-494f-a4c5-3776371cdc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224286471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2224286471
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2318475379
Short name T570
Test name
Test status
Simulation time 33769110 ps
CPU time 1.57 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 200008 kb
Host smart-e37f6b68-3ec9-4bd3-b6b5-76b637e812a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318475379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2318475379
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2274231014
Short name T62
Test name
Test status
Simulation time 260237318 ps
CPU time 1.37 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 199952 kb
Host smart-07819ae2-17b7-4c00-9439-0f794ca3a65a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274231014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2274231014
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1913193598
Short name T595
Test name
Test status
Simulation time 183914596 ps
CPU time 3.01 seconds
Started May 12 01:30:07 PM PDT 24
Finished May 12 01:30:10 PM PDT 24
Peak memory 199956 kb
Host smart-2d6633cc-edce-4135-a23c-56cd98c9d017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913193598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1913193598
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.449306621
Short name T495
Test name
Test status
Simulation time 56718922 ps
CPU time 3.47 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 215364 kb
Host smart-4882460f-85f3-4e0e-aa9b-26deb91ac64e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449306621 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.449306621
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2174984477
Short name T80
Test name
Test status
Simulation time 17269236 ps
CPU time 0.77 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 199128 kb
Host smart-e5a1956d-ac69-45fe-9fe4-4f906127bcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174984477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2174984477
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.441055935
Short name T598
Test name
Test status
Simulation time 29928640 ps
CPU time 0.62 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 195204 kb
Host smart-6be3e174-55ba-4384-b1e5-0ada21b1bb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441055935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.441055935
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2945060549
Short name T535
Test name
Test status
Simulation time 442776508 ps
CPU time 2.26 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200036 kb
Host smart-affee2de-f93d-463f-a1d0-b33140b5f9c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945060549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2945060549
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1878210342
Short name T556
Test name
Test status
Simulation time 288572984 ps
CPU time 3.87 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200080 kb
Host smart-ea95a24c-e9d0-4f80-8fb7-e56d924f75f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878210342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1878210342
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1002003712
Short name T113
Test name
Test status
Simulation time 1152097556 ps
CPU time 4.23 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200128 kb
Host smart-e9e05d37-4bf5-4600-b226-107dfacd9ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002003712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1002003712
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.253420910
Short name T586
Test name
Test status
Simulation time 37453796 ps
CPU time 2.17 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200196 kb
Host smart-d2ab403e-6921-40ee-a5eb-083b1e77b5ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253420910 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.253420910
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4114029925
Short name T541
Test name
Test status
Simulation time 53994234 ps
CPU time 0.9 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 199348 kb
Host smart-b67e17a2-61f0-473b-bc5e-ef6b6fcb1633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114029925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4114029925
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3831420887
Short name T575
Test name
Test status
Simulation time 36095767 ps
CPU time 0.57 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:18 PM PDT 24
Peak memory 194932 kb
Host smart-d99429aa-544e-4b84-b869-c45d7f0569f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831420887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3831420887
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2264789830
Short name T494
Test name
Test status
Simulation time 400407063 ps
CPU time 1.84 seconds
Started May 12 01:30:11 PM PDT 24
Finished May 12 01:30:13 PM PDT 24
Peak memory 199900 kb
Host smart-46efa12e-0ed6-4e7c-a839-31c9051ccda5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264789830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2264789830
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1886516323
Short name T566
Test name
Test status
Simulation time 123973370 ps
CPU time 2.66 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 199968 kb
Host smart-d452250f-2b1b-4425-bcb6-cedbde38ed4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886516323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1886516323
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4196965672
Short name T112
Test name
Test status
Simulation time 94751228 ps
CPU time 1.87 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200092 kb
Host smart-851f5198-beae-4a62-ae1d-661320d81935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196965672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4196965672
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1989003368
Short name T546
Test name
Test status
Simulation time 83499248 ps
CPU time 1.34 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 200136 kb
Host smart-c1ff28d9-762d-4c15-8868-77de5073611d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989003368 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1989003368
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3113072972
Short name T89
Test name
Test status
Simulation time 53748760 ps
CPU time 0.83 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 199836 kb
Host smart-f7bb05e7-611d-4a1f-92e8-761057524407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113072972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3113072972
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3752038520
Short name T565
Test name
Test status
Simulation time 46754308 ps
CPU time 0.56 seconds
Started May 12 01:30:10 PM PDT 24
Finished May 12 01:30:11 PM PDT 24
Peak memory 194868 kb
Host smart-2a6c83ae-34c9-4a67-9cd2-9aaad0fec5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752038520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3752038520
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4227286455
Short name T59
Test name
Test status
Simulation time 451560141 ps
CPU time 2.03 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 199932 kb
Host smart-97e08978-3879-4f47-b89d-1f0888e2d4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227286455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4227286455
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1051517051
Short name T498
Test name
Test status
Simulation time 232763403 ps
CPU time 2.89 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 199752 kb
Host smart-fab9bf52-b025-4f9a-b69e-e9cb003b3667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051517051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1051517051
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.716962097
Short name T109
Test name
Test status
Simulation time 387399618 ps
CPU time 3.97 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:27 PM PDT 24
Peak memory 200012 kb
Host smart-a088db0c-88f0-43b8-bb32-86f20630fa06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716962097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.716962097
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.420417780
Short name T552
Test name
Test status
Simulation time 97569490729 ps
CPU time 412.06 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:37:13 PM PDT 24
Peak memory 215716 kb
Host smart-842f3f96-35b0-44b6-a64c-123cc5f14685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420417780 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.420417780
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3617970174
Short name T589
Test name
Test status
Simulation time 89083422 ps
CPU time 0.85 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 199344 kb
Host smart-218eb800-753e-4f55-9513-54bdfa1bb061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617970174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3617970174
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1472697625
Short name T479
Test name
Test status
Simulation time 13525751 ps
CPU time 0.6 seconds
Started May 12 01:30:12 PM PDT 24
Finished May 12 01:30:13 PM PDT 24
Peak memory 194896 kb
Host smart-adcd382c-cab4-4188-9141-258a626696df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472697625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1472697625
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2255382937
Short name T518
Test name
Test status
Simulation time 171002222 ps
CPU time 2.08 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 200084 kb
Host smart-f5ae25ca-c819-4bbe-90f0-86db0b111bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255382937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2255382937
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.45427617
Short name T543
Test name
Test status
Simulation time 79209302 ps
CPU time 1.85 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 200076 kb
Host smart-72c85453-0dae-48f4-a1d3-29e4a58d1cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45427617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.45427617
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1299931367
Short name T110
Test name
Test status
Simulation time 220619172 ps
CPU time 4.42 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 199996 kb
Host smart-b6a86b89-58e5-4cb6-82d6-411c60a0f603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299931367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1299931367
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3579871327
Short name T522
Test name
Test status
Simulation time 94284435 ps
CPU time 2.3 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 200080 kb
Host smart-1786bbda-ff34-421d-a05a-726217412f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579871327 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3579871327
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.569082755
Short name T93
Test name
Test status
Simulation time 65691992 ps
CPU time 0.73 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 197992 kb
Host smart-725383f9-bb2f-47c2-b0a8-ae1b0d3d8ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569082755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.569082755
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2119154788
Short name T537
Test name
Test status
Simulation time 66571620 ps
CPU time 0.64 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 194844 kb
Host smart-ebedb413-63ab-4bbe-8050-faa6977a1e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119154788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2119154788
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3129072894
Short name T571
Test name
Test status
Simulation time 148172411 ps
CPU time 2.33 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 199864 kb
Host smart-e9a442e2-c334-43c0-ab5a-67bfff405334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129072894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3129072894
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3092790618
Short name T562
Test name
Test status
Simulation time 79703009 ps
CPU time 4.01 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 200144 kb
Host smart-89081d59-f5f7-4e52-abdc-f28223a913fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092790618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3092790618
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.743944069
Short name T510
Test name
Test status
Simulation time 737563802 ps
CPU time 1.73 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200028 kb
Host smart-b15c0e65-e58d-4ff2-8961-ae1d25607e17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743944069 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.743944069
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2469384086
Short name T83
Test name
Test status
Simulation time 34407297 ps
CPU time 0.96 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 199704 kb
Host smart-81ed9568-655a-47a7-a3b3-874f47b72bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469384086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2469384086
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.888185435
Short name T534
Test name
Test status
Simulation time 48117037 ps
CPU time 0.62 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 194864 kb
Host smart-831b6f27-cc44-477c-844c-35d0c7e8f600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888185435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.888185435
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1736156139
Short name T572
Test name
Test status
Simulation time 29586235 ps
CPU time 1.05 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 198636 kb
Host smart-7dd47169-fad4-42b7-81e9-53c56c5124c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736156139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1736156139
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.948954948
Short name T560
Test name
Test status
Simulation time 93953491 ps
CPU time 1.45 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 199984 kb
Host smart-e7a51346-6a72-4d24-9c60-fe1730c7ce05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948954948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.948954948
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1497848205
Short name T584
Test name
Test status
Simulation time 219392805 ps
CPU time 1.81 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 199984 kb
Host smart-ac044782-2733-45b5-a928-0cb1c284ce78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497848205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1497848205
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3253942974
Short name T60
Test name
Test status
Simulation time 63019410 ps
CPU time 1.08 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 199948 kb
Host smart-d61212a5-3862-45bd-8b8e-e84808801af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253942974 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3253942974
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2923769218
Short name T486
Test name
Test status
Simulation time 172639237 ps
CPU time 0.75 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 198072 kb
Host smart-dcdc5c7a-449d-41a8-a393-4ddb838d10d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923769218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2923769218
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.4193684329
Short name T480
Test name
Test status
Simulation time 13679999 ps
CPU time 0.57 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 194968 kb
Host smart-ed4c4cdd-13c5-46b3-964f-5e7cac220636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193684329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4193684329
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1527226025
Short name T564
Test name
Test status
Simulation time 83983717 ps
CPU time 2.1 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 200100 kb
Host smart-18fe188c-48df-4940-830f-1aa3cdfb8553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527226025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1527226025
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4010030947
Short name T508
Test name
Test status
Simulation time 604448843 ps
CPU time 3.6 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:28 PM PDT 24
Peak memory 200064 kb
Host smart-368b7c10-79d4-460a-93ec-d50ec2e699c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010030947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4010030947
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.698806211
Short name T531
Test name
Test status
Simulation time 357119574 ps
CPU time 2.43 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 199552 kb
Host smart-3531956d-d80b-40da-ba3f-911904d3504d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698806211 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.698806211
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2687171131
Short name T569
Test name
Test status
Simulation time 26134685 ps
CPU time 0.82 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 199844 kb
Host smart-05903f68-50a2-4f0f-aaca-31ab22ef10a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687171131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2687171131
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1714480620
Short name T580
Test name
Test status
Simulation time 22999099 ps
CPU time 0.62 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 194900 kb
Host smart-87a95478-b0c6-44bc-b159-f583f7203eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714480620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1714480620
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3852383388
Short name T507
Test name
Test status
Simulation time 45259680 ps
CPU time 1.13 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 199856 kb
Host smart-7700b937-6d88-4ff3-9cba-0ad8dc541db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852383388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3852383388
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1398912496
Short name T526
Test name
Test status
Simulation time 127145651 ps
CPU time 3.43 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 200100 kb
Host smart-6591ab8b-e793-4a72-8120-3f0768ebb72c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398912496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1398912496
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2928184621
Short name T594
Test name
Test status
Simulation time 482246221 ps
CPU time 1.73 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 200016 kb
Host smart-fb3db249-6e6a-49b4-a31c-d5539c380cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928184621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2928184621
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3335529110
Short name T481
Test name
Test status
Simulation time 2080307081 ps
CPU time 3.39 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 200056 kb
Host smart-4d5a442f-6ecf-424e-9b70-394d01f388aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335529110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3335529110
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2759412997
Short name T509
Test name
Test status
Simulation time 320631191 ps
CPU time 13.84 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200236 kb
Host smart-424fae8e-543f-47ab-ab16-b5c474ae06fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759412997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2759412997
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1280543135
Short name T529
Test name
Test status
Simulation time 19425641 ps
CPU time 0.74 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:46 PM PDT 24
Peak memory 197776 kb
Host smart-c1cae2f5-99dc-4175-9e81-14bda93ffb70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280543135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1280543135
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1418952137
Short name T57
Test name
Test status
Simulation time 72851189 ps
CPU time 1.31 seconds
Started May 12 01:29:56 PM PDT 24
Finished May 12 01:29:58 PM PDT 24
Peak memory 199792 kb
Host smart-50f1cbdc-9228-4d38-9b88-7179fb9dbc77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418952137 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1418952137
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.118343089
Short name T557
Test name
Test status
Simulation time 23876100 ps
CPU time 0.81 seconds
Started May 12 01:29:45 PM PDT 24
Finished May 12 01:29:46 PM PDT 24
Peak memory 199884 kb
Host smart-37275528-8182-4a32-b051-8b4323f4acce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118343089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.118343089
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.410989832
Short name T542
Test name
Test status
Simulation time 56212204 ps
CPU time 0.64 seconds
Started May 12 01:29:57 PM PDT 24
Finished May 12 01:29:58 PM PDT 24
Peak memory 194836 kb
Host smart-523b04e4-70e5-4e4a-9a9d-2ab57d3f6503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410989832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.410989832
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.697087322
Short name T525
Test name
Test status
Simulation time 320250925 ps
CPU time 1.79 seconds
Started May 12 01:29:56 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 199808 kb
Host smart-78827d3d-d5b3-4be0-bbfd-10be557959e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697087322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.697087322
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3662868321
Short name T61
Test name
Test status
Simulation time 117749842 ps
CPU time 1.77 seconds
Started May 12 01:29:57 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 199940 kb
Host smart-c9336451-aeee-46bb-a5e6-2437de83865f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662868321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3662868321
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1637340492
Short name T551
Test name
Test status
Simulation time 179392816 ps
CPU time 1.82 seconds
Started May 12 01:29:57 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 199976 kb
Host smart-e39a2830-7454-4346-b241-daf150c3c29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637340492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1637340492
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1506243537
Short name T528
Test name
Test status
Simulation time 18327427 ps
CPU time 0.65 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 194856 kb
Host smart-0428931c-607a-46ba-b4b1-e8eec219076f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506243537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1506243537
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1140489196
Short name T520
Test name
Test status
Simulation time 12491038 ps
CPU time 0.6 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:23 PM PDT 24
Peak memory 194792 kb
Host smart-a03ebdb6-a98e-4a81-a5ca-e1d54a78c9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140489196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1140489196
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1614481635
Short name T73
Test name
Test status
Simulation time 14937104 ps
CPU time 0.61 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 194336 kb
Host smart-0aea070d-776f-4ab5-a24d-ed1d91a24813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614481635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1614481635
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.675354165
Short name T596
Test name
Test status
Simulation time 58480043 ps
CPU time 0.57 seconds
Started May 12 01:30:17 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 194908 kb
Host smart-2454f81e-6e9e-4171-821c-ac5978fecf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675354165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.675354165
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1150834126
Short name T491
Test name
Test status
Simulation time 12915234 ps
CPU time 0.58 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194952 kb
Host smart-37426a88-52b7-462f-ae4a-fb305f247604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150834126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1150834126
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3021515006
Short name T488
Test name
Test status
Simulation time 13048699 ps
CPU time 0.57 seconds
Started May 12 01:30:19 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 194848 kb
Host smart-e0ec594a-5aa0-45e7-82ee-0d39025792f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021515006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3021515006
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.581637211
Short name T593
Test name
Test status
Simulation time 15199202 ps
CPU time 0.63 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194952 kb
Host smart-4127bfd3-ef4b-459a-8f5d-d4fe97c04591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581637211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.581637211
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.660665963
Short name T483
Test name
Test status
Simulation time 11444896 ps
CPU time 0.59 seconds
Started May 12 01:30:20 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 194904 kb
Host smart-5594d08d-502b-4e70-a31c-c43741084e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660665963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.660665963
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.106707031
Short name T547
Test name
Test status
Simulation time 58285414 ps
CPU time 0.62 seconds
Started May 12 01:30:18 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 194964 kb
Host smart-9a8c7d2d-e8e5-4fcd-8cd3-c12c9a04bc1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106707031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.106707031
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.383358385
Short name T577
Test name
Test status
Simulation time 12281470 ps
CPU time 0.57 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194784 kb
Host smart-e6ec99b0-0661-46af-bb71-8f6d23998e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383358385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.383358385
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2019886883
Short name T87
Test name
Test status
Simulation time 637279762 ps
CPU time 3.5 seconds
Started May 12 01:29:57 PM PDT 24
Finished May 12 01:30:00 PM PDT 24
Peak memory 199892 kb
Host smart-e654f6a3-8f83-4cd0-8038-3c864d21194a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019886883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2019886883
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.17240372
Short name T92
Test name
Test status
Simulation time 1055845670 ps
CPU time 16.55 seconds
Started May 12 01:29:50 PM PDT 24
Finished May 12 01:30:07 PM PDT 24
Peak memory 199048 kb
Host smart-5a11885f-14a4-4978-9e19-d6f2ef52bf6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.17240372
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.894942950
Short name T501
Test name
Test status
Simulation time 13315560 ps
CPU time 0.69 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:45 PM PDT 24
Peak memory 197812 kb
Host smart-2d20a7e5-6aea-4059-a0f0-9d1da7345abd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894942950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.894942950
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3158323933
Short name T523
Test name
Test status
Simulation time 36973568 ps
CPU time 1.09 seconds
Started May 12 01:29:49 PM PDT 24
Finished May 12 01:29:51 PM PDT 24
Peak memory 199828 kb
Host smart-5cae80d0-6a22-4c56-b5e7-073c9c026b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158323933 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3158323933
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4231087374
Short name T588
Test name
Test status
Simulation time 31987566 ps
CPU time 0.67 seconds
Started May 12 01:29:47 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 197744 kb
Host smart-c593cf27-d3aa-4ae3-a2a3-301731de9df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231087374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.4231087374
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3641116435
Short name T502
Test name
Test status
Simulation time 19465716 ps
CPU time 0.57 seconds
Started May 12 01:29:43 PM PDT 24
Finished May 12 01:29:44 PM PDT 24
Peak memory 194832 kb
Host smart-fe3ab9b8-c6d6-4354-9fe7-38184931966b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641116435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3641116435
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1071440525
Short name T533
Test name
Test status
Simulation time 156579475 ps
CPU time 1.82 seconds
Started May 12 01:29:57 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 199744 kb
Host smart-667fff7d-8f84-451f-bfa1-411343cdf1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071440525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1071440525
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.567372229
Short name T504
Test name
Test status
Simulation time 72666064 ps
CPU time 1.6 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:47 PM PDT 24
Peak memory 200104 kb
Host smart-7f933c47-0da2-4cae-a06f-08a9483468fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567372229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.567372229
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1658349862
Short name T50
Test name
Test status
Simulation time 315142729 ps
CPU time 1.9 seconds
Started May 12 01:29:44 PM PDT 24
Finished May 12 01:29:47 PM PDT 24
Peak memory 200132 kb
Host smart-d8385423-a52e-4072-8f6c-c1bee5f39de8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658349862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1658349862
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2874046314
Short name T514
Test name
Test status
Simulation time 50943882 ps
CPU time 0.62 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194924 kb
Host smart-a0c30f98-d95a-4927-8349-c8b932a0be7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874046314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2874046314
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2708192180
Short name T539
Test name
Test status
Simulation time 14785275 ps
CPU time 0.59 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194888 kb
Host smart-4d83e3dd-e814-4bf3-bb30-ff40df752db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708192180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2708192180
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3093593852
Short name T574
Test name
Test status
Simulation time 15285759 ps
CPU time 0.6 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194968 kb
Host smart-eea26752-8887-4df7-8a30-10b041a1ec41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093593852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3093593852
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3622566474
Short name T549
Test name
Test status
Simulation time 19092272 ps
CPU time 0.63 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194824 kb
Host smart-c1d1f613-6d00-431c-982a-07fc5b804c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622566474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3622566474
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3190969656
Short name T582
Test name
Test status
Simulation time 94681436 ps
CPU time 0.59 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194664 kb
Host smart-ee38ac26-d58d-4052-8cfa-854ddf889d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190969656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3190969656
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1047590016
Short name T536
Test name
Test status
Simulation time 26355313 ps
CPU time 0.61 seconds
Started May 12 01:30:24 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194888 kb
Host smart-5249137d-9da5-449d-a0da-4f3b0e9c560d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047590016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1047590016
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3846332663
Short name T482
Test name
Test status
Simulation time 30852981 ps
CPU time 0.61 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194768 kb
Host smart-d40a6513-aa91-4971-a025-0724ac22d9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846332663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3846332663
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1785963354
Short name T591
Test name
Test status
Simulation time 20675756 ps
CPU time 0.58 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194884 kb
Host smart-4ee4ac2e-3d47-48d7-8004-f27e57bc1871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785963354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1785963354
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2874440207
Short name T599
Test name
Test status
Simulation time 14538668 ps
CPU time 0.62 seconds
Started May 12 01:30:25 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 195004 kb
Host smart-2d67c65c-4a1d-4899-b947-8b3f08a9f116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874440207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2874440207
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.682980587
Short name T524
Test name
Test status
Simulation time 40903058 ps
CPU time 0.62 seconds
Started May 12 01:30:24 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194892 kb
Host smart-7da32b0d-c098-4b66-91b3-265309e4a319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682980587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.682980587
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2627495977
Short name T558
Test name
Test status
Simulation time 216893433 ps
CPU time 3.51 seconds
Started May 12 01:29:48 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 199984 kb
Host smart-3bb0f73a-f057-433e-a53b-116cb75388ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627495977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2627495977
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.495496070
Short name T521
Test name
Test status
Simulation time 12423876088 ps
CPU time 15.81 seconds
Started May 12 01:29:48 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 199700 kb
Host smart-3c49ffa0-e227-4625-a742-2035523b1ece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495496070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.495496070
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1575330153
Short name T94
Test name
Test status
Simulation time 45062214 ps
CPU time 1 seconds
Started May 12 01:29:48 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 199392 kb
Host smart-142ed196-eebe-45ed-9c05-3e4dce4c9443
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575330153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1575330153
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.943813434
Short name T573
Test name
Test status
Simulation time 100497859 ps
CPU time 1.18 seconds
Started May 12 01:29:50 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 200168 kb
Host smart-8a59fa5f-8568-4db5-83d9-56396b9b16e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943813434 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.943813434
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3833997765
Short name T79
Test name
Test status
Simulation time 57838771 ps
CPU time 0.9 seconds
Started May 12 01:29:48 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 199364 kb
Host smart-a5468742-7d51-4a59-8241-d8c28cd391f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833997765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3833997765
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4016644488
Short name T72
Test name
Test status
Simulation time 15227702 ps
CPU time 0.61 seconds
Started May 12 01:29:49 PM PDT 24
Finished May 12 01:29:50 PM PDT 24
Peak memory 194812 kb
Host smart-f33f7aab-faea-4672-bc78-6dc000ab0850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016644488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4016644488
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.651350122
Short name T485
Test name
Test status
Simulation time 24014962 ps
CPU time 1.07 seconds
Started May 12 01:29:48 PM PDT 24
Finished May 12 01:29:50 PM PDT 24
Peak memory 199916 kb
Host smart-89c94fc1-cad9-4933-8c42-0347174b4189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651350122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.651350122
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1205393209
Short name T21
Test name
Test status
Simulation time 187790003 ps
CPU time 3.43 seconds
Started May 12 01:29:50 PM PDT 24
Finished May 12 01:29:54 PM PDT 24
Peak memory 199988 kb
Host smart-663654ed-f286-4882-b076-bbf60daf52f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205393209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1205393209
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2432297434
Short name T108
Test name
Test status
Simulation time 228910144 ps
CPU time 4.19 seconds
Started May 12 01:29:51 PM PDT 24
Finished May 12 01:29:55 PM PDT 24
Peak memory 200300 kb
Host smart-56e49736-f631-4150-a6f0-9541cf3d5f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432297434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2432297434
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4238107754
Short name T597
Test name
Test status
Simulation time 23353274 ps
CPU time 0.6 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194956 kb
Host smart-547eaf9b-3388-4b0d-939e-fa1ccd1d6d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238107754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4238107754
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.82196778
Short name T493
Test name
Test status
Simulation time 49123388 ps
CPU time 0.58 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194796 kb
Host smart-65294d9b-c17b-42e0-b0db-8f35e441a614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82196778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.82196778
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1393820503
Short name T487
Test name
Test status
Simulation time 62072254 ps
CPU time 0.61 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194824 kb
Host smart-8ac0dfd2-182f-423d-9d30-d0ae24be7276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393820503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1393820503
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1721957866
Short name T553
Test name
Test status
Simulation time 33641808 ps
CPU time 0.66 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194888 kb
Host smart-700b096b-177c-4903-a581-b037ef066413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721957866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1721957866
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3815745455
Short name T592
Test name
Test status
Simulation time 13189032 ps
CPU time 0.57 seconds
Started May 12 01:30:25 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 194884 kb
Host smart-491f388a-0492-4b7a-b606-7ad9b57ea134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815745455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3815745455
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4227451569
Short name T530
Test name
Test status
Simulation time 14828857 ps
CPU time 0.57 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194892 kb
Host smart-c1c75c02-402e-4154-96cb-38da867af5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227451569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4227451569
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1003437365
Short name T496
Test name
Test status
Simulation time 17098630 ps
CPU time 0.64 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194936 kb
Host smart-375a0841-accb-43a6-bd62-a7e75eeb7e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003437365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1003437365
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1898414723
Short name T563
Test name
Test status
Simulation time 24503896 ps
CPU time 0.64 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194860 kb
Host smart-1f0c5713-a37f-49c6-8597-e06af498e94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898414723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1898414723
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3455246871
Short name T519
Test name
Test status
Simulation time 32944901 ps
CPU time 0.59 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 194816 kb
Host smart-ff4a7e3d-b31c-4f42-b9ad-7e1b0a0096ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455246871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3455246871
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.380900377
Short name T568
Test name
Test status
Simulation time 47965590 ps
CPU time 0.61 seconds
Started May 12 01:30:21 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 194912 kb
Host smart-4524aaf4-feaa-4ef7-9ad1-f79564aa340f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380900377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.380900377
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1925321260
Short name T548
Test name
Test status
Simulation time 249408909 ps
CPU time 1.9 seconds
Started May 12 01:29:56 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200044 kb
Host smart-2facdea6-7bf9-4707-aeb0-1e30d6452eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925321260 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1925321260
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1598314248
Short name T567
Test name
Test status
Simulation time 54155863 ps
CPU time 0.69 seconds
Started May 12 01:29:52 PM PDT 24
Finished May 12 01:29:53 PM PDT 24
Peak memory 197440 kb
Host smart-952fc88b-92a2-4154-abd4-dae42f689d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598314248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1598314248
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.426881810
Short name T71
Test name
Test status
Simulation time 116443949 ps
CPU time 0.58 seconds
Started May 12 01:29:51 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 194880 kb
Host smart-87bf9f4a-706e-4994-9273-43c0f7d702b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426881810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.426881810
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.235130491
Short name T505
Test name
Test status
Simulation time 621590259 ps
CPU time 2.43 seconds
Started May 12 01:29:53 PM PDT 24
Finished May 12 01:29:55 PM PDT 24
Peak memory 200008 kb
Host smart-50483300-62f2-4af9-9f68-e4f502a54f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235130491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.235130491
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1933968686
Short name T490
Test name
Test status
Simulation time 290131171 ps
CPU time 2.13 seconds
Started May 12 01:29:52 PM PDT 24
Finished May 12 01:29:54 PM PDT 24
Peak memory 200056 kb
Host smart-b2974241-d169-4ce7-9f23-3cb3f067419f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933968686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1933968686
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1256777894
Short name T512
Test name
Test status
Simulation time 139722355 ps
CPU time 3.97 seconds
Started May 12 01:29:51 PM PDT 24
Finished May 12 01:29:55 PM PDT 24
Peak memory 200020 kb
Host smart-fdc8ba37-7438-4618-8667-ac0987c65ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256777894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1256777894
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.542711676
Short name T517
Test name
Test status
Simulation time 37213382 ps
CPU time 1.23 seconds
Started May 12 01:29:58 PM PDT 24
Finished May 12 01:30:00 PM PDT 24
Peak memory 199900 kb
Host smart-4ad19197-dec7-4aaa-8d91-ebf55314f78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542711676 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.542711676
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2193019564
Short name T82
Test name
Test status
Simulation time 135718080 ps
CPU time 1 seconds
Started May 12 01:30:02 PM PDT 24
Finished May 12 01:30:03 PM PDT 24
Peak memory 199392 kb
Host smart-51ed4a90-c568-4cc2-8d60-3da5d21cfa53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193019564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2193019564
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3910003063
Short name T579
Test name
Test status
Simulation time 52148804 ps
CPU time 0.56 seconds
Started May 12 01:29:55 PM PDT 24
Finished May 12 01:29:56 PM PDT 24
Peak memory 194860 kb
Host smart-eeaf009e-6ab6-417e-8bb2-598a32fa8907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910003063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3910003063
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3197844980
Short name T503
Test name
Test status
Simulation time 73408005 ps
CPU time 1.69 seconds
Started May 12 01:29:58 PM PDT 24
Finished May 12 01:30:01 PM PDT 24
Peak memory 200064 kb
Host smart-919b7d19-7bf9-4e73-a437-c26ae4669436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197844980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3197844980
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2279244211
Short name T581
Test name
Test status
Simulation time 177887745 ps
CPU time 3.74 seconds
Started May 12 01:29:55 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200048 kb
Host smart-07a5ac8f-57f6-4454-88b8-4fefdd3e213e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279244211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2279244211
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4208986871
Short name T52
Test name
Test status
Simulation time 83265326 ps
CPU time 1.79 seconds
Started May 12 01:29:56 PM PDT 24
Finished May 12 01:29:58 PM PDT 24
Peak memory 200020 kb
Host smart-8f0100ef-2762-420a-b8ae-b6823a5816d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208986871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.4208986871
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.552953195
Short name T492
Test name
Test status
Simulation time 125665527 ps
CPU time 2.11 seconds
Started May 12 01:30:00 PM PDT 24
Finished May 12 01:30:03 PM PDT 24
Peak memory 200100 kb
Host smart-6240ec9c-7ce3-40c2-8533-a63c0a2767f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552953195 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.552953195
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2339780514
Short name T58
Test name
Test status
Simulation time 87291909 ps
CPU time 0.72 seconds
Started May 12 01:30:00 PM PDT 24
Finished May 12 01:30:01 PM PDT 24
Peak memory 198176 kb
Host smart-126604d2-b0da-460d-b913-b9949ef8f110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339780514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2339780514
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2971379888
Short name T527
Test name
Test status
Simulation time 57327570 ps
CPU time 0.65 seconds
Started May 12 01:30:02 PM PDT 24
Finished May 12 01:30:03 PM PDT 24
Peak memory 194920 kb
Host smart-8189053e-37a4-4a7b-a21d-426a47882ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971379888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2971379888
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1889746304
Short name T484
Test name
Test status
Simulation time 35238273 ps
CPU time 1.63 seconds
Started May 12 01:30:02 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 199940 kb
Host smart-bb1782ba-35bc-4e27-a3ee-44a376f3a619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889746304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1889746304
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1296155387
Short name T561
Test name
Test status
Simulation time 279727366 ps
CPU time 3.38 seconds
Started May 12 01:30:03 PM PDT 24
Finished May 12 01:30:07 PM PDT 24
Peak memory 200340 kb
Host smart-7573011c-6e80-458c-a8de-293c02f84bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296155387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1296155387
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3379362536
Short name T587
Test name
Test status
Simulation time 155836599 ps
CPU time 1.84 seconds
Started May 12 01:30:03 PM PDT 24
Finished May 12 01:30:05 PM PDT 24
Peak memory 200344 kb
Host smart-339b1bf7-3d94-48ba-b19f-a4a81d2fff31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379362536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3379362536
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4012495116
Short name T77
Test name
Test status
Simulation time 65297554 ps
CPU time 1.09 seconds
Started May 12 01:30:03 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 199880 kb
Host smart-b9539dd8-d043-417e-8362-6531a862efe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012495116 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4012495116
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4251855561
Short name T86
Test name
Test status
Simulation time 122691390 ps
CPU time 0.88 seconds
Started May 12 01:30:04 PM PDT 24
Finished May 12 01:30:05 PM PDT 24
Peak memory 199368 kb
Host smart-b29decf3-9413-4c5e-905f-5a2f828848fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251855561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4251855561
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4256830924
Short name T545
Test name
Test status
Simulation time 22204064 ps
CPU time 0.59 seconds
Started May 12 01:30:02 PM PDT 24
Finished May 12 01:30:03 PM PDT 24
Peak memory 194884 kb
Host smart-cbdd7ac5-851f-40ff-b150-f228edce1da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256830924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4256830924
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4101425353
Short name T555
Test name
Test status
Simulation time 101557250 ps
CPU time 1.26 seconds
Started May 12 01:30:04 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 199984 kb
Host smart-07400aac-d46b-42b8-8817-646d360f9b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101425353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4101425353
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.74550312
Short name T516
Test name
Test status
Simulation time 345244435 ps
CPU time 2.9 seconds
Started May 12 01:29:59 PM PDT 24
Finished May 12 01:30:02 PM PDT 24
Peak memory 199948 kb
Host smart-e09f1cb3-6a6d-4574-bd54-fa9e606dba23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74550312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.74550312
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3104705619
Short name T114
Test name
Test status
Simulation time 180714829 ps
CPU time 1.69 seconds
Started May 12 01:30:02 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 200168 kb
Host smart-e3f57f5a-ea82-418c-ac59-2cbbbe1d8809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104705619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3104705619
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1764078133
Short name T600
Test name
Test status
Simulation time 86719383 ps
CPU time 1.35 seconds
Started May 12 01:30:06 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 200012 kb
Host smart-f2a11db7-bb87-4bba-9115-f29ae7b1455e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764078133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1764078133
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.897949672
Short name T74
Test name
Test status
Simulation time 34826354 ps
CPU time 0.95 seconds
Started May 12 01:30:05 PM PDT 24
Finished May 12 01:30:07 PM PDT 24
Peak memory 199760 kb
Host smart-aceda02e-35cc-4844-9af9-f35708730cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897949672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.897949672
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1664085958
Short name T544
Test name
Test status
Simulation time 35305604 ps
CPU time 0.6 seconds
Started May 12 01:30:04 PM PDT 24
Finished May 12 01:30:05 PM PDT 24
Peak memory 194804 kb
Host smart-625d3a9d-e5cd-41c4-9ab9-98016b4713bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664085958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1664085958
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4264728270
Short name T489
Test name
Test status
Simulation time 113456190 ps
CPU time 2.28 seconds
Started May 12 01:30:06 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 200000 kb
Host smart-2527cc1c-e16d-4755-92b3-03c14b6a3a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264728270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4264728270
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1754504563
Short name T56
Test name
Test status
Simulation time 471741625 ps
CPU time 2.79 seconds
Started May 12 01:30:03 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 200276 kb
Host smart-d2c9bdc1-7b0a-4727-acc5-406e8ac6db09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754504563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1754504563
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.533965678
Short name T578
Test name
Test status
Simulation time 225812375 ps
CPU time 3.19 seconds
Started May 12 01:30:04 PM PDT 24
Finished May 12 01:30:08 PM PDT 24
Peak memory 200064 kb
Host smart-50947e82-ea4a-4746-80e6-e1ca40ed8bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533965678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.533965678
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3954139579
Short name T423
Test name
Test status
Simulation time 10649465 ps
CPU time 0.56 seconds
Started May 12 01:33:31 PM PDT 24
Finished May 12 01:33:32 PM PDT 24
Peak memory 195212 kb
Host smart-3ba722c7-bd76-46f2-9437-96da470532f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954139579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3954139579
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.544669702
Short name T145
Test name
Test status
Simulation time 706218975 ps
CPU time 9.93 seconds
Started May 12 01:33:27 PM PDT 24
Finished May 12 01:33:38 PM PDT 24
Peak memory 200620 kb
Host smart-227116e9-2d50-4adb-b555-663bcdbb56d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544669702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.544669702
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.796740668
Short name T455
Test name
Test status
Simulation time 2811632722 ps
CPU time 2.92 seconds
Started May 12 01:33:26 PM PDT 24
Finished May 12 01:33:30 PM PDT 24
Peak memory 200716 kb
Host smart-d29641ea-3aca-4ff8-9e72-a25a62b35072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796740668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.796740668
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2536012119
Short name T350
Test name
Test status
Simulation time 18426331530 ps
CPU time 1581.42 seconds
Started May 12 01:33:27 PM PDT 24
Finished May 12 01:59:49 PM PDT 24
Peak memory 761248 kb
Host smart-43ec6ff1-964e-427e-a59a-f71b46c0975f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536012119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2536012119
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.933226341
Short name T153
Test name
Test status
Simulation time 2368054090 ps
CPU time 11.8 seconds
Started May 12 01:33:26 PM PDT 24
Finished May 12 01:33:38 PM PDT 24
Peak memory 200632 kb
Host smart-162f5d35-5ff3-4073-bffe-95150ad3945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933226341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.933226341
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3054587053
Short name T27
Test name
Test status
Simulation time 125234648 ps
CPU time 0.82 seconds
Started May 12 01:33:27 PM PDT 24
Finished May 12 01:33:29 PM PDT 24
Peak memory 218732 kb
Host smart-57480eae-2c6a-4907-958d-cc11bf735a5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054587053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3054587053
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1267561091
Short name T35
Test name
Test status
Simulation time 460197613 ps
CPU time 5.26 seconds
Started May 12 01:33:28 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 200512 kb
Host smart-ca4a77f4-a9fe-409c-bafc-69552916e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267561091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1267561091
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4193985319
Short name T69
Test name
Test status
Simulation time 28780691151 ps
CPU time 1889.64 seconds
Started May 12 01:33:29 PM PDT 24
Finished May 12 02:05:00 PM PDT 24
Peak memory 798792 kb
Host smart-eeed0398-40f0-47d2-8cf0-5f9bc29e148d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193985319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4193985319
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1428138023
Short name T282
Test name
Test status
Simulation time 53681924 ps
CPU time 1.18 seconds
Started May 12 01:33:29 PM PDT 24
Finished May 12 01:33:31 PM PDT 24
Peak memory 200620 kb
Host smart-3ea9ae5b-f252-423d-aba0-411ce72e6fbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428138023 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1428138023
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3692375958
Short name T340
Test name
Test status
Simulation time 220603673318 ps
CPU time 551.02 seconds
Started May 12 01:33:27 PM PDT 24
Finished May 12 01:42:39 PM PDT 24
Peak memory 200616 kb
Host smart-b3241043-37a8-40e6-ba51-ca3da6d84642
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692375958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3692375958
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2508747943
Short name T372
Test name
Test status
Simulation time 14224545 ps
CPU time 0.63 seconds
Started May 12 01:33:33 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 196248 kb
Host smart-47042421-68f9-4305-97b8-982ee571d283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508747943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2508747943
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3293470894
Short name T434
Test name
Test status
Simulation time 213166486 ps
CPU time 2.5 seconds
Started May 12 01:33:31 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 200632 kb
Host smart-221d09fe-19f2-45c1-a667-9b3dba9b4b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293470894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3293470894
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.160639243
Short name T278
Test name
Test status
Simulation time 3380341272 ps
CPU time 41.21 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:34:12 PM PDT 24
Peak memory 200708 kb
Host smart-7a08d155-9790-44b3-a06e-043b5dd2dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160639243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.160639243
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3323611568
Short name T152
Test name
Test status
Simulation time 7420987376 ps
CPU time 497.47 seconds
Started May 12 01:33:31 PM PDT 24
Finished May 12 01:41:49 PM PDT 24
Peak memory 654516 kb
Host smart-b7c16780-04ee-4059-b6f5-ae300a4416cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323611568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3323611568
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1003978125
Short name T191
Test name
Test status
Simulation time 2822891113 ps
CPU time 14.25 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:33:45 PM PDT 24
Peak memory 200692 kb
Host smart-efd8a808-2c60-4502-8769-97af2ac19cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003978125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1003978125
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2605627349
Short name T198
Test name
Test status
Simulation time 176844368 ps
CPU time 5.89 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:33:36 PM PDT 24
Peak memory 200640 kb
Host smart-220b54c5-ba5e-4200-9fa2-44b293fbce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605627349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2605627349
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1895393482
Short name T380
Test name
Test status
Simulation time 210423346 ps
CPU time 1.19 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:33:31 PM PDT 24
Peak memory 199416 kb
Host smart-516e3a7b-848a-44e5-9caa-8383443e3f7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895393482 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1895393482
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2223888650
Short name T467
Test name
Test status
Simulation time 28353620674 ps
CPU time 408.56 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:40:24 PM PDT 24
Peak memory 200576 kb
Host smart-9af4228b-9a53-441d-a57f-8eb030f1a2e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223888650 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2223888650
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3588163491
Short name T126
Test name
Test status
Simulation time 19000682 ps
CPU time 0.57 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:33:49 PM PDT 24
Peak memory 195296 kb
Host smart-fec75189-3382-46da-a374-89557642f3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588163491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3588163491
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3838522060
Short name T215
Test name
Test status
Simulation time 84472103 ps
CPU time 3.81 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:33:52 PM PDT 24
Peak memory 200568 kb
Host smart-64e91251-fd76-4568-acc3-a7067872ff49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838522060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3838522060
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3933299464
Short name T167
Test name
Test status
Simulation time 1504692046 ps
CPU time 29.1 seconds
Started May 12 01:33:51 PM PDT 24
Finished May 12 01:34:20 PM PDT 24
Peak memory 200328 kb
Host smart-30152685-542c-46aa-8293-56d03c54c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933299464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3933299464
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3175554596
Short name T227
Test name
Test status
Simulation time 2792987405 ps
CPU time 768.75 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:46:37 PM PDT 24
Peak memory 762276 kb
Host smart-46b2628c-7c41-47ee-a2f9-70f333653d28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175554596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3175554596
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.680378510
Short name T338
Test name
Test status
Simulation time 1116141672 ps
CPU time 55.71 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200492 kb
Host smart-620aae9f-2a59-4993-9d4c-926ba57a5c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680378510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.680378510
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1005472130
Short name T142
Test name
Test status
Simulation time 1460424961 ps
CPU time 2.9 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:33:53 PM PDT 24
Peak memory 200624 kb
Host smart-1af9de85-e85d-4222-9bf7-b4d615e3d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005472130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1005472130
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1504655072
Short name T267
Test name
Test status
Simulation time 160197853 ps
CPU time 0.99 seconds
Started May 12 01:33:48 PM PDT 24
Finished May 12 01:33:50 PM PDT 24
Peak memory 198920 kb
Host smart-901a44d7-086d-4055-9569-1de5495ed7ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504655072 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1504655072
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1589804646
Short name T244
Test name
Test status
Simulation time 104990531247 ps
CPU time 455.27 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:41:26 PM PDT 24
Peak memory 200600 kb
Host smart-83b27a99-b8a3-4859-ac19-31ba1f883963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589804646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1589804646
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.56545378
Short name T474
Test name
Test status
Simulation time 43935359 ps
CPU time 0.56 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:33:49 PM PDT 24
Peak memory 195908 kb
Host smart-eb3d4302-4fd5-4bd7-a916-b9d5eb5ea45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56545378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.56545378
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3400057571
Short name T358
Test name
Test status
Simulation time 3505389836 ps
CPU time 17.09 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:34:05 PM PDT 24
Peak memory 200764 kb
Host smart-b96ba393-ac8b-4547-8050-f287c4bb2d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400057571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3400057571
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3582691153
Short name T386
Test name
Test status
Simulation time 129550628 ps
CPU time 2.97 seconds
Started May 12 01:33:51 PM PDT 24
Finished May 12 01:33:54 PM PDT 24
Peak memory 200332 kb
Host smart-39b6cbf7-1239-481a-b5af-c52f93d36896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582691153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3582691153
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1247498687
Short name T433
Test name
Test status
Simulation time 1220523397 ps
CPU time 222.46 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:37:29 PM PDT 24
Peak memory 465596 kb
Host smart-4b5e2e76-577d-4e70-b1d6-fc0ed0838466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247498687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1247498687
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.427065528
Short name T334
Test name
Test status
Simulation time 19118441979 ps
CPU time 87.42 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:35:16 PM PDT 24
Peak memory 200628 kb
Host smart-eef89a68-f60d-496b-a71b-2b25a614509d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427065528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.427065528
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1001816451
Short name T123
Test name
Test status
Simulation time 152883155 ps
CPU time 3 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:33:52 PM PDT 24
Peak memory 200628 kb
Host smart-c2c00c5b-6801-4bbe-a397-4c36f6fc4010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001816451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1001816451
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2917892327
Short name T472
Test name
Test status
Simulation time 152049273 ps
CPU time 2.08 seconds
Started May 12 01:33:48 PM PDT 24
Finished May 12 01:33:51 PM PDT 24
Peak memory 200508 kb
Host smart-786e3c8d-d441-4d65-a96b-7e7f12c78514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917892327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2917892327
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1599974942
Short name T379
Test name
Test status
Simulation time 61048107 ps
CPU time 1.39 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:33:51 PM PDT 24
Peak memory 200528 kb
Host smart-ff6a023a-4729-425b-81f6-f4a1458de0eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599974942 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1599974942
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3815562161
Short name T311
Test name
Test status
Simulation time 48005260913 ps
CPU time 476.74 seconds
Started May 12 01:33:51 PM PDT 24
Finished May 12 01:41:48 PM PDT 24
Peak memory 200660 kb
Host smart-05547659-0dea-4308-99f8-8a0777512836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815562161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3815562161
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4129266050
Short name T292
Test name
Test status
Simulation time 3130522638 ps
CPU time 36.69 seconds
Started May 12 01:33:50 PM PDT 24
Finished May 12 01:34:27 PM PDT 24
Peak memory 227656 kb
Host smart-4ee2b7bb-ba73-464e-bc3b-f6d223171d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129266050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4129266050
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1584000056
Short name T139
Test name
Test status
Simulation time 3448363026 ps
CPU time 901.92 seconds
Started May 12 01:33:50 PM PDT 24
Finished May 12 01:48:53 PM PDT 24
Peak memory 760796 kb
Host smart-8d26c237-5c4b-4402-9742-0715db06172e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1584000056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1584000056
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1552882225
Short name T401
Test name
Test status
Simulation time 9874960602 ps
CPU time 67.52 seconds
Started May 12 01:33:45 PM PDT 24
Finished May 12 01:34:54 PM PDT 24
Peak memory 200736 kb
Host smart-8880e817-c165-47fe-ad38-e83820014030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552882225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1552882225
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1814606847
Short name T175
Test name
Test status
Simulation time 406217468 ps
CPU time 4.87 seconds
Started May 12 01:33:47 PM PDT 24
Finished May 12 01:33:54 PM PDT 24
Peak memory 200584 kb
Host smart-0053ce4c-3510-465b-abc5-c842fa74ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814606847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1814606847
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1667307779
Short name T381
Test name
Test status
Simulation time 59313094 ps
CPU time 1.16 seconds
Started May 12 01:33:51 PM PDT 24
Finished May 12 01:33:53 PM PDT 24
Peak memory 200524 kb
Host smart-a38ea33d-ccd6-4e60-a7b3-31e3f8fc9b60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667307779 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1667307779
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3643305440
Short name T226
Test name
Test status
Simulation time 109401473532 ps
CPU time 500.79 seconds
Started May 12 01:33:52 PM PDT 24
Finished May 12 01:42:13 PM PDT 24
Peak memory 200624 kb
Host smart-24822123-108a-4b47-9d86-d138fe9d41c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643305440 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3643305440
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2246192601
Short name T173
Test name
Test status
Simulation time 39049577 ps
CPU time 0.58 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:33:57 PM PDT 24
Peak memory 197060 kb
Host smart-a60cea21-6c4a-4dd8-8af2-3e7bfa0506f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246192601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2246192601
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3001946808
Short name T230
Test name
Test status
Simulation time 4434252023 ps
CPU time 72.06 seconds
Started May 12 01:33:48 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 248572 kb
Host smart-cd7228f0-dc58-4294-9838-dd4a4ce68351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001946808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3001946808
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1759372038
Short name T418
Test name
Test status
Simulation time 9061594626 ps
CPU time 37.94 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:34:28 PM PDT 24
Peak memory 200784 kb
Host smart-6b27144e-a939-46f8-86fc-f773034485f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759372038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1759372038
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1408486153
Short name T128
Test name
Test status
Simulation time 3679259746 ps
CPU time 896.98 seconds
Started May 12 01:33:49 PM PDT 24
Finished May 12 01:48:47 PM PDT 24
Peak memory 674464 kb
Host smart-f50199eb-2eb1-4e1c-944e-4e2c32a6765b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408486153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1408486153
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3556697240
Short name T384
Test name
Test status
Simulation time 7068862444 ps
CPU time 105.89 seconds
Started May 12 01:33:50 PM PDT 24
Finished May 12 01:35:37 PM PDT 24
Peak memory 200732 kb
Host smart-d3715e61-e0a2-4236-8c10-d836ed9804d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556697240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3556697240
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2963825395
Short name T240
Test name
Test status
Simulation time 107923979 ps
CPU time 3.39 seconds
Started May 12 01:33:50 PM PDT 24
Finished May 12 01:33:54 PM PDT 24
Peak memory 200536 kb
Host smart-3a24a0d2-9af8-4ef8-9db3-aec5126db88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963825395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2963825395
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2820961054
Short name T325
Test name
Test status
Simulation time 56021674 ps
CPU time 1.03 seconds
Started May 12 01:33:48 PM PDT 24
Finished May 12 01:33:50 PM PDT 24
Peak memory 200092 kb
Host smart-d4d9c267-b011-4be9-9b0c-614add0925c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820961054 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2820961054
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.228019220
Short name T129
Test name
Test status
Simulation time 31177209840 ps
CPU time 441.01 seconds
Started May 12 01:33:50 PM PDT 24
Finished May 12 01:41:12 PM PDT 24
Peak memory 200628 kb
Host smart-0b05209c-0966-4cbf-a869-99d3ed1e4aa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228019220 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.228019220
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1218862945
Short name T388
Test name
Test status
Simulation time 15227770 ps
CPU time 0.65 seconds
Started May 12 01:34:02 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 195264 kb
Host smart-30250008-8865-442b-bcba-702515d40b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218862945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1218862945
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4278252078
Short name T373
Test name
Test status
Simulation time 175742215 ps
CPU time 8.74 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:34:06 PM PDT 24
Peak memory 208820 kb
Host smart-33e08d3a-acf9-442b-9a82-3a75255fb486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278252078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4278252078
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2805124667
Short name T314
Test name
Test status
Simulation time 433905817 ps
CPU time 11.46 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:34:07 PM PDT 24
Peak memory 200580 kb
Host smart-c35a12ed-f5ec-4c24-afb9-5ea3cc782516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805124667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2805124667
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.570061773
Short name T179
Test name
Test status
Simulation time 3920743592 ps
CPU time 236.7 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:37:57 PM PDT 24
Peak memory 649736 kb
Host smart-25057939-de49-40f9-954d-613149851798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570061773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.570061773
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3244073423
Short name T466
Test name
Test status
Simulation time 16550716408 ps
CPU time 135.4 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:36:11 PM PDT 24
Peak memory 200728 kb
Host smart-720070d5-9a5f-426d-ab31-6b02047009ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244073423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3244073423
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3617426897
Short name T207
Test name
Test status
Simulation time 655680385 ps
CPU time 8.07 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200568 kb
Host smart-0165d881-1802-4be6-a65f-510b8acaa9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617426897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3617426897
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2448186752
Short name T445
Test name
Test status
Simulation time 25935550 ps
CPU time 1.02 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 199040 kb
Host smart-1897c229-593b-49c8-bcca-e3c337bd63da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448186752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2448186752
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.464583823
Short name T348
Test name
Test status
Simulation time 7278333021 ps
CPU time 399.44 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:40:35 PM PDT 24
Peak memory 200652 kb
Host smart-8e64c373-167e-413a-a6a3-306b588dc2f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464583823 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.464583823
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4041783494
Short name T404
Test name
Test status
Simulation time 37654645 ps
CPU time 0.57 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:34:00 PM PDT 24
Peak memory 195180 kb
Host smart-9dd3f954-e895-42cd-b55c-41b2c9499eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041783494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4041783494
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2718236707
Short name T305
Test name
Test status
Simulation time 1024730849 ps
CPU time 28.85 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 216120 kb
Host smart-dc95ddcc-bd04-42dd-a6d0-0cde88c7b16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718236707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2718236707
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3892760328
Short name T104
Test name
Test status
Simulation time 2371732023 ps
CPU time 46.85 seconds
Started May 12 01:33:55 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 200760 kb
Host smart-5f672e20-3e58-40f7-82fa-91c602885b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892760328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3892760328
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3535013439
Short name T458
Test name
Test status
Simulation time 353604580 ps
CPU time 30.76 seconds
Started May 12 01:33:58 PM PDT 24
Finished May 12 01:34:29 PM PDT 24
Peak memory 302672 kb
Host smart-782b3add-0d78-4cff-b43e-5257206d964d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535013439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3535013439
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1546614140
Short name T463
Test name
Test status
Simulation time 99373699624 ps
CPU time 104.6 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:35:45 PM PDT 24
Peak memory 200680 kb
Host smart-436a1e46-7223-493c-b042-e77024130e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546614140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1546614140
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1630346425
Short name T376
Test name
Test status
Simulation time 91840744 ps
CPU time 3.4 seconds
Started May 12 01:33:54 PM PDT 24
Finished May 12 01:33:58 PM PDT 24
Peak memory 200568 kb
Host smart-2053a33f-fb38-495e-8ef1-bbd9a04ce8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630346425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1630346425
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2495377302
Short name T22
Test name
Test status
Simulation time 132453811 ps
CPU time 0.7 seconds
Started May 12 01:33:58 PM PDT 24
Finished May 12 01:33:59 PM PDT 24
Peak memory 195996 kb
Host smart-4dae2299-b85f-453a-bbf3-ec2ba9775489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495377302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2495377302
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3711392399
Short name T428
Test name
Test status
Simulation time 159997669 ps
CPU time 1.08 seconds
Started May 12 01:33:54 PM PDT 24
Finished May 12 01:33:56 PM PDT 24
Peak memory 200428 kb
Host smart-993e1193-d3dd-4012-be20-b35c709bea4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711392399 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3711392399
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2482269367
Short name T228
Test name
Test status
Simulation time 96649592805 ps
CPU time 430.17 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:41:08 PM PDT 24
Peak memory 200688 kb
Host smart-5132906c-24b0-417a-af6f-d8350c70144c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482269367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2482269367
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2990994408
Short name T182
Test name
Test status
Simulation time 26061260 ps
CPU time 0.62 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:02 PM PDT 24
Peak memory 196164 kb
Host smart-e78330b3-5360-4e18-8a4c-45c0e28a6c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990994408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2990994408
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.58685108
Short name T450
Test name
Test status
Simulation time 85844163 ps
CPU time 4.92 seconds
Started May 12 01:34:01 PM PDT 24
Finished May 12 01:34:07 PM PDT 24
Peak memory 200568 kb
Host smart-8d5b1664-e0e9-45f8-9ba1-c7ba3873a0db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58685108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.58685108
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3714200573
Short name T288
Test name
Test status
Simulation time 385752683 ps
CPU time 6.91 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:08 PM PDT 24
Peak memory 200524 kb
Host smart-717af133-f2fb-4d66-89fe-50512167c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714200573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3714200573
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.997987252
Short name T97
Test name
Test status
Simulation time 10823773059 ps
CPU time 469.62 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:41:50 PM PDT 24
Peak memory 439220 kb
Host smart-5cc0ae9d-6812-4a82-967a-d6e6ff7f1e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997987252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.997987252
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.99928598
Short name T55
Test name
Test status
Simulation time 67483070 ps
CPU time 3.45 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200508 kb
Host smart-76603e5b-83de-4695-a5fb-cb06c94aa3d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99928598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.99928598
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1101009155
Short name T242
Test name
Test status
Simulation time 3667843100 ps
CPU time 51.89 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:53 PM PDT 24
Peak memory 200680 kb
Host smart-dd8c7271-c014-4acb-b76e-a3f3ef18dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101009155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1101009155
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2707992346
Short name T477
Test name
Test status
Simulation time 633455066 ps
CPU time 5.01 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200568 kb
Host smart-3b6259a2-d706-4177-a7ea-8ac31def2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707992346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2707992346
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.15582705
Short name T263
Test name
Test status
Simulation time 319122604 ps
CPU time 0.9 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:34:01 PM PDT 24
Peak memory 199088 kb
Host smart-9fa9f5e3-69d9-4696-8c94-673343dbd27f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15582705 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_hmac_vectors.15582705
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.719320548
Short name T125
Test name
Test status
Simulation time 33244996419 ps
CPU time 478.09 seconds
Started May 12 01:34:01 PM PDT 24
Finished May 12 01:41:59 PM PDT 24
Peak memory 200616 kb
Host smart-c89d7716-ffb9-4fa0-b789-b1a743545317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719320548 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.719320548
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1948122177
Short name T146
Test name
Test status
Simulation time 44084739 ps
CPU time 0.6 seconds
Started May 12 01:34:01 PM PDT 24
Finished May 12 01:34:02 PM PDT 24
Peak memory 196288 kb
Host smart-470693ff-ecb9-4eae-94f8-571945020d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948122177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1948122177
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.327472530
Short name T119
Test name
Test status
Simulation time 5351326703 ps
CPU time 47.63 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:50 PM PDT 24
Peak memory 220048 kb
Host smart-e35166b8-dc89-4780-a564-350c548cf0e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327472530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.327472530
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3808245721
Short name T398
Test name
Test status
Simulation time 1929122313 ps
CPU time 50.11 seconds
Started May 12 01:33:58 PM PDT 24
Finished May 12 01:34:49 PM PDT 24
Peak memory 200632 kb
Host smart-4a2b3609-9b0d-4597-82f1-08507fa477a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808245721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3808245721
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2080148797
Short name T421
Test name
Test status
Simulation time 5834479110 ps
CPU time 744.74 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:46:27 PM PDT 24
Peak memory 717564 kb
Host smart-75799e1a-3922-4c7e-9b1c-2cea00f5d2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080148797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2080148797
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3240084909
Short name T121
Test name
Test status
Simulation time 2737285096 ps
CPU time 79.57 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:35:20 PM PDT 24
Peak memory 200720 kb
Host smart-f69703a1-5198-4c1a-81f2-1eb5188dc5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240084909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3240084909
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3517571179
Short name T233
Test name
Test status
Simulation time 976565338 ps
CPU time 5.6 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:34:05 PM PDT 24
Peak memory 200548 kb
Host smart-1fafc2e3-2fdc-42c3-b8e6-33bf80a4a762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517571179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3517571179
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3270511625
Short name T285
Test name
Test status
Simulation time 27671457 ps
CPU time 0.97 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:33:59 PM PDT 24
Peak memory 198952 kb
Host smart-7a55b8f6-328a-4985-8d2d-9fc88cd7a417
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270511625 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3270511625
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3535024937
Short name T359
Test name
Test status
Simulation time 105758368162 ps
CPU time 475.87 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:41:55 PM PDT 24
Peak memory 200676 kb
Host smart-58211ba0-5c81-48e6-aa5b-a1d393646e3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535024937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3535024937
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.4028723082
Short name T349
Test name
Test status
Simulation time 39568630 ps
CPU time 0.61 seconds
Started May 12 01:34:01 PM PDT 24
Finished May 12 01:34:02 PM PDT 24
Peak memory 197000 kb
Host smart-8cd5a354-2bc1-4bde-9571-72ac52ab68e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028723082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4028723082
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.610751842
Short name T319
Test name
Test status
Simulation time 967749341 ps
CPU time 62.93 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:35:06 PM PDT 24
Peak memory 241076 kb
Host smart-45b2d5f6-703e-4f73-859e-91533b194770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610751842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.610751842
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3843055525
Short name T475
Test name
Test status
Simulation time 1673677013 ps
CPU time 22.31 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:34:26 PM PDT 24
Peak memory 200568 kb
Host smart-dc4b98dc-dbbd-48ca-b2ac-683fa1e8e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843055525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3843055525
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3890583621
Short name T320
Test name
Test status
Simulation time 2685131865 ps
CPU time 658.5 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 708796 kb
Host smart-bb82a644-8984-4cb6-99f4-4d740849b9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890583621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3890583621
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1310773639
Short name T247
Test name
Test status
Simulation time 2025689234 ps
CPU time 14.89 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:16 PM PDT 24
Peak memory 200404 kb
Host smart-fdf2f1bb-4c66-4818-b27d-ba5d5b5f1bf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310773639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1310773639
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2706274453
Short name T412
Test name
Test status
Simulation time 1071875917 ps
CPU time 64.28 seconds
Started May 12 01:33:57 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 200596 kb
Host smart-85807a20-2a2c-43cb-b6ca-0f90793172b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706274453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2706274453
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2858645712
Short name T336
Test name
Test status
Simulation time 2149325276 ps
CPU time 4.37 seconds
Started May 12 01:33:58 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200844 kb
Host smart-735897c3-8592-4943-9899-80662ae5e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858645712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2858645712
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2036078815
Short name T148
Test name
Test status
Simulation time 34789713 ps
CPU time 1.27 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:02 PM PDT 24
Peak memory 200524 kb
Host smart-71e4003f-22d0-4171-bf23-6817e5723421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036078815 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2036078815
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1714206760
Short name T170
Test name
Test status
Simulation time 13157878999 ps
CPU time 411.79 seconds
Started May 12 01:33:59 PM PDT 24
Finished May 12 01:40:52 PM PDT 24
Peak memory 200688 kb
Host smart-605b54f3-4643-4e05-b859-7cab9b7c5837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714206760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1714206760
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2410062462
Short name T17
Test name
Test status
Simulation time 43182761 ps
CPU time 0.61 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:34:04 PM PDT 24
Peak memory 196344 kb
Host smart-3a1a38ab-d02d-44f1-965c-f7d4d98533ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410062462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2410062462
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2722244851
Short name T473
Test name
Test status
Simulation time 532429403 ps
CPU time 27.96 seconds
Started May 12 01:34:00 PM PDT 24
Finished May 12 01:34:28 PM PDT 24
Peak memory 208984 kb
Host smart-252cd892-d721-4ddd-8831-418c2bf41854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722244851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2722244851
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.732120360
Short name T246
Test name
Test status
Simulation time 49919340060 ps
CPU time 44.46 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:53 PM PDT 24
Peak memory 200676 kb
Host smart-a6ca0e55-40cb-418d-9929-f68d8fb5cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732120360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.732120360
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3404909902
Short name T330
Test name
Test status
Simulation time 13978533808 ps
CPU time 77.46 seconds
Started May 12 01:34:01 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 200716 kb
Host smart-5710f3af-1a3f-44c2-a558-baf63280c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404909902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3404909902
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1300732117
Short name T40
Test name
Test status
Simulation time 775993999 ps
CPU time 3.01 seconds
Started May 12 01:34:02 PM PDT 24
Finished May 12 01:34:05 PM PDT 24
Peak memory 200532 kb
Host smart-87d54984-a4b6-4e95-a9ea-c251194cadfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300732117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1300732117
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.3529237599
Short name T20
Test name
Test status
Simulation time 89489676321 ps
CPU time 426.19 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:41:10 PM PDT 24
Peak memory 225448 kb
Host smart-3902f871-bd71-4163-8766-2fc586878e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529237599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.3529237599
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2285007202
Short name T306
Test name
Test status
Simulation time 57864414 ps
CPU time 1.13 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 200140 kb
Host smart-e5019837-ccb1-4dca-babf-391e8180a654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285007202 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2285007202
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.448961531
Short name T290
Test name
Test status
Simulation time 15293340399 ps
CPU time 449.31 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:41:37 PM PDT 24
Peak memory 200564 kb
Host smart-b73cd239-651c-4b87-8ab7-bef61f7f0f18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448961531 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.448961531
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3737378316
Short name T16
Test name
Test status
Simulation time 39314603 ps
CPU time 0.6 seconds
Started May 12 01:33:36 PM PDT 24
Finished May 12 01:33:37 PM PDT 24
Peak memory 197040 kb
Host smart-646800a0-8e1d-4bcd-b518-9fd60f411354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737378316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3737378316
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4086584197
Short name T48
Test name
Test status
Simulation time 724664522 ps
CPU time 22.61 seconds
Started May 12 01:33:28 PM PDT 24
Finished May 12 01:33:51 PM PDT 24
Peak memory 233272 kb
Host smart-f947a841-4282-40e3-8519-e2d4d5b9372d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086584197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4086584197
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2453387902
Short name T249
Test name
Test status
Simulation time 2772908617 ps
CPU time 66.98 seconds
Started May 12 01:33:31 PM PDT 24
Finished May 12 01:34:39 PM PDT 24
Peak memory 200632 kb
Host smart-79f76417-5e19-4ddc-a225-7f1d36e18ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453387902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2453387902
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1561593414
Short name T296
Test name
Test status
Simulation time 3133275051 ps
CPU time 200.59 seconds
Started May 12 01:33:30 PM PDT 24
Finished May 12 01:36:52 PM PDT 24
Peak memory 604100 kb
Host smart-0cf6bc5c-2388-4606-a9f3-f06f1e9ee49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561593414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1561593414
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1855589396
Short name T471
Test name
Test status
Simulation time 5998995140 ps
CPU time 81.23 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:34:56 PM PDT 24
Peak memory 200728 kb
Host smart-831e87da-42a0-48ab-9900-7980a25273af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855589396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1855589396
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2245722815
Short name T29
Test name
Test status
Simulation time 124847319 ps
CPU time 0.89 seconds
Started May 12 01:33:34 PM PDT 24
Finished May 12 01:33:36 PM PDT 24
Peak memory 218740 kb
Host smart-4f6aee60-f052-4a73-a9b1-6e51db22ca1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245722815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2245722815
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2005039804
Short name T256
Test name
Test status
Simulation time 295218091 ps
CPU time 3.62 seconds
Started May 12 01:33:29 PM PDT 24
Finished May 12 01:33:33 PM PDT 24
Peak memory 200524 kb
Host smart-e09a5869-4532-4570-97e8-81a5960d2066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005039804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2005039804
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2599602784
Short name T286
Test name
Test status
Simulation time 56361002 ps
CPU time 1.08 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 200092 kb
Host smart-ec7a85ea-b4a3-4d7b-8d77-990f372dfe13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599602784 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2599602784
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2988119542
Short name T324
Test name
Test status
Simulation time 56634048661 ps
CPU time 518.92 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:42:15 PM PDT 24
Peak memory 200660 kb
Host smart-4d953799-1c71-48ea-9d77-be3b616951a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988119542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2988119542
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2328745068
Short name T214
Test name
Test status
Simulation time 28796277 ps
CPU time 0.61 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 197024 kb
Host smart-a5a8662e-4d8f-4ce4-9a97-3f4240c79fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328745068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2328745068
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1711567641
Short name T34
Test name
Test status
Simulation time 338188539 ps
CPU time 5.35 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:34:11 PM PDT 24
Peak memory 216828 kb
Host smart-334b9380-1944-4b1f-8eb6-4585f0e4de94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711567641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1711567641
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2592342659
Short name T157
Test name
Test status
Simulation time 89047127 ps
CPU time 1.12 seconds
Started May 12 01:34:02 PM PDT 24
Finished May 12 01:34:04 PM PDT 24
Peak memory 200464 kb
Host smart-e698c481-6740-49e5-a35d-f424e38b6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592342659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2592342659
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1449029380
Short name T429
Test name
Test status
Simulation time 5938852402 ps
CPU time 805.98 seconds
Started May 12 01:34:02 PM PDT 24
Finished May 12 01:47:29 PM PDT 24
Peak memory 746148 kb
Host smart-104a3fdc-574f-4fd5-aff4-378acac5bb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449029380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1449029380
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4094364406
Short name T189
Test name
Test status
Simulation time 739831398 ps
CPU time 41.56 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:50 PM PDT 24
Peak memory 200524 kb
Host smart-dbcf7395-1270-4a7a-9f00-a814536c9680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094364406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4094364406
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4054352392
Short name T464
Test name
Test status
Simulation time 72447248 ps
CPU time 1.95 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:10 PM PDT 24
Peak memory 200516 kb
Host smart-62af58eb-1e57-4143-8e3e-58cdbeda68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054352392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4054352392
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.4256228648
Short name T144
Test name
Test status
Simulation time 141522708 ps
CPU time 0.96 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:34:06 PM PDT 24
Peak memory 199912 kb
Host smart-c3bccc0f-4115-48d2-9b52-7b80f0add736
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256228648 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.4256228648
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2951465668
Short name T417
Test name
Test status
Simulation time 26839410138 ps
CPU time 482.48 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:42:07 PM PDT 24
Peak memory 200684 kb
Host smart-26027be1-78cd-4ca4-8682-4694b84e154e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951465668 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2951465668
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.654711726
Short name T392
Test name
Test status
Simulation time 50756940 ps
CPU time 0.64 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:34:06 PM PDT 24
Peak memory 196960 kb
Host smart-708f028d-5a64-4b6c-ae6d-1a29ccf4b090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654711726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.654711726
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2987477641
Short name T46
Test name
Test status
Simulation time 677977345 ps
CPU time 9.29 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:34:15 PM PDT 24
Peak memory 208800 kb
Host smart-630e9a0a-1f9c-400a-ade8-2233a8539eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987477641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2987477641
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.125836476
Short name T192
Test name
Test status
Simulation time 1405822078 ps
CPU time 15.55 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:34:21 PM PDT 24
Peak memory 200524 kb
Host smart-6b01ecda-59c8-4ce8-8c17-84b5fc4604ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125836476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.125836476
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1523196254
Short name T254
Test name
Test status
Simulation time 2513160398 ps
CPU time 708.51 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:45:56 PM PDT 24
Peak memory 738256 kb
Host smart-ac75478b-dfec-460a-b4a0-7a29d26603e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523196254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1523196254
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3607215347
Short name T333
Test name
Test status
Simulation time 5019046985 ps
CPU time 17.87 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:34:23 PM PDT 24
Peak memory 200596 kb
Host smart-73a63a1e-84b3-4cd3-9b74-c5a455ebaa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607215347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3607215347
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2244144395
Short name T1
Test name
Test status
Simulation time 364927876 ps
CPU time 5.86 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:34:12 PM PDT 24
Peak memory 200504 kb
Host smart-fce6083a-f9e4-49cf-9c85-234d9e01cce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244144395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2244144395
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3806313881
Short name T200
Test name
Test status
Simulation time 51137663 ps
CPU time 1.08 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:34:05 PM PDT 24
Peak memory 200072 kb
Host smart-5b7c3ace-ea23-4835-81a3-6c9741543bd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806313881 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3806313881
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.939867665
Short name T181
Test name
Test status
Simulation time 259053892100 ps
CPU time 523.35 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:42:48 PM PDT 24
Peak memory 200588 kb
Host smart-259e570a-9245-4ac0-b11a-1eb708a71ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939867665 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.939867665
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3249066611
Short name T268
Test name
Test status
Simulation time 14495682 ps
CPU time 0.62 seconds
Started May 12 01:34:10 PM PDT 24
Finished May 12 01:34:11 PM PDT 24
Peak memory 196336 kb
Host smart-47144ae1-350c-4857-b7c8-d7ba0ac8699a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249066611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3249066611
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1656712451
Short name T438
Test name
Test status
Simulation time 8337331266 ps
CPU time 43.69 seconds
Started May 12 01:34:03 PM PDT 24
Finished May 12 01:34:47 PM PDT 24
Peak memory 221288 kb
Host smart-67af1cf5-6a30-44a1-a235-988e095cdc30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656712451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1656712451
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3199982810
Short name T426
Test name
Test status
Simulation time 7799699621 ps
CPU time 54.63 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 200644 kb
Host smart-49d1d982-9222-4890-8933-410eb11261ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199982810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3199982810
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.285909678
Short name T269
Test name
Test status
Simulation time 884133373 ps
CPU time 220.05 seconds
Started May 12 01:34:04 PM PDT 24
Finished May 12 01:37:45 PM PDT 24
Peak memory 477084 kb
Host smart-38f407d5-e544-4fc6-a6d5-fe54a7f3e079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285909678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.285909678
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1897351614
Short name T275
Test name
Test status
Simulation time 12087746105 ps
CPU time 120.11 seconds
Started May 12 01:34:06 PM PDT 24
Finished May 12 01:36:07 PM PDT 24
Peak memory 200628 kb
Host smart-70f9f423-fe85-43b3-a1d8-661a9ff3f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897351614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1897351614
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4160081449
Short name T375
Test name
Test status
Simulation time 360880624 ps
CPU time 4.6 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:13 PM PDT 24
Peak memory 200612 kb
Host smart-245e9005-cafc-4ff6-acde-cbdd1413ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160081449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4160081449
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.4013875687
Short name T210
Test name
Test status
Simulation time 54996565 ps
CPU time 1.27 seconds
Started May 12 01:34:09 PM PDT 24
Finished May 12 01:34:11 PM PDT 24
Peak memory 200484 kb
Host smart-a6fe9130-227e-4898-ae05-3998b9d1f028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013875687 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.4013875687
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1435361474
Short name T355
Test name
Test status
Simulation time 53041343518 ps
CPU time 498.69 seconds
Started May 12 01:34:05 PM PDT 24
Finished May 12 01:42:24 PM PDT 24
Peak memory 200652 kb
Host smart-853ae932-24a1-48c7-b640-f8982c2f040a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435361474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1435361474
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.170042702
Short name T328
Test name
Test status
Simulation time 34914366 ps
CPU time 0.56 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:34:08 PM PDT 24
Peak memory 195296 kb
Host smart-0455719b-243f-441f-90ba-e67e751cc5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170042702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.170042702
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4075848258
Short name T183
Test name
Test status
Simulation time 1371428426 ps
CPU time 42.84 seconds
Started May 12 01:34:09 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 241480 kb
Host smart-ed0c6e9b-a81c-45c4-b7ab-1e4f124cd894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075848258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4075848258
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1557067154
Short name T211
Test name
Test status
Simulation time 2889030739 ps
CPU time 39.29 seconds
Started May 12 01:34:09 PM PDT 24
Finished May 12 01:34:49 PM PDT 24
Peak memory 200652 kb
Host smart-2b5e215b-a05c-425a-8265-2ae9d48e8ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557067154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1557067154
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.931605218
Short name T131
Test name
Test status
Simulation time 2511585991 ps
CPU time 103.04 seconds
Started May 12 01:34:09 PM PDT 24
Finished May 12 01:35:53 PM PDT 24
Peak memory 443716 kb
Host smart-fd893c43-0dcb-4c69-9a50-2c70d8267687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931605218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.931605218
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2881594781
Short name T454
Test name
Test status
Simulation time 2308905566 ps
CPU time 12.09 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:21 PM PDT 24
Peak memory 200704 kb
Host smart-5ca7a7a0-158f-4f22-a8a6-6e29f52c9afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881594781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2881594781
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3952154074
Short name T409
Test name
Test status
Simulation time 664351244 ps
CPU time 7.27 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:34:15 PM PDT 24
Peak memory 200540 kb
Host smart-498ab333-1544-44a2-b22f-af1af32ac664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952154074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3952154074
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1843547929
Short name T277
Test name
Test status
Simulation time 362529865 ps
CPU time 1.08 seconds
Started May 12 01:34:08 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 200036 kb
Host smart-6282427e-9554-4d51-bc03-acebf7d9ea64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843547929 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1843547929
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2717145514
Short name T393
Test name
Test status
Simulation time 22813317346 ps
CPU time 421.63 seconds
Started May 12 01:34:07 PM PDT 24
Finished May 12 01:41:09 PM PDT 24
Peak memory 200672 kb
Host smart-3ae4e0d7-798c-4b38-810a-a96e0dd66ace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717145514 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2717145514
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3828605781
Short name T239
Test name
Test status
Simulation time 15398969 ps
CPU time 0.59 seconds
Started May 12 01:34:11 PM PDT 24
Finished May 12 01:34:11 PM PDT 24
Peak memory 195884 kb
Host smart-4cbd93ee-1560-4360-bbf4-11a4dfdbf9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828605781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3828605781
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3528023564
Short name T310
Test name
Test status
Simulation time 331547346 ps
CPU time 21.26 seconds
Started May 12 01:34:12 PM PDT 24
Finished May 12 01:34:33 PM PDT 24
Peak memory 232572 kb
Host smart-3c69f465-8786-4ccb-be2a-bd72407788cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528023564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3528023564
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.67758907
Short name T431
Test name
Test status
Simulation time 2575246547 ps
CPU time 48.9 seconds
Started May 12 01:34:11 PM PDT 24
Finished May 12 01:35:00 PM PDT 24
Peak memory 200692 kb
Host smart-528bcd0b-a516-4fa4-94f5-eb7306a813e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67758907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.67758907
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2967774272
Short name T365
Test name
Test status
Simulation time 9270159793 ps
CPU time 632.97 seconds
Started May 12 01:34:12 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 723604 kb
Host smart-381f6534-4f6b-49a5-a624-407b2018a03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967774272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2967774272
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_long_msg.727302194
Short name T281
Test name
Test status
Simulation time 3988677286 ps
CPU time 75.52 seconds
Started May 12 01:34:13 PM PDT 24
Finished May 12 01:35:29 PM PDT 24
Peak memory 200712 kb
Host smart-4195da1e-e923-460e-b816-7464ea93e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727302194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.727302194
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2018748090
Short name T335
Test name
Test status
Simulation time 9308916805 ps
CPU time 6.4 seconds
Started May 12 01:34:11 PM PDT 24
Finished May 12 01:34:18 PM PDT 24
Peak memory 200668 kb
Host smart-d38e6b3b-c045-4ddf-bd10-124278d1dfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018748090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2018748090
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2585833927
Short name T323
Test name
Test status
Simulation time 129331095 ps
CPU time 1.27 seconds
Started May 12 01:34:12 PM PDT 24
Finished May 12 01:34:14 PM PDT 24
Peak memory 200612 kb
Host smart-0775ce57-7bf7-4aa0-960e-5d00e8ca59d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585833927 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2585833927
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3435995390
Short name T206
Test name
Test status
Simulation time 26568260661 ps
CPU time 476.36 seconds
Started May 12 01:34:17 PM PDT 24
Finished May 12 01:42:14 PM PDT 24
Peak memory 200620 kb
Host smart-d16cb2fe-5bab-4bd6-9804-202b661b79ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435995390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3435995390
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.178694102
Short name T465
Test name
Test status
Simulation time 838898193 ps
CPU time 4.37 seconds
Started May 12 01:34:14 PM PDT 24
Finished May 12 01:34:19 PM PDT 24
Peak memory 200616 kb
Host smart-1db9c34b-381d-4678-b733-0762bf59a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178694102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.178694102
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4261988437
Short name T197
Test name
Test status
Simulation time 31380255 ps
CPU time 0.62 seconds
Started May 12 01:34:17 PM PDT 24
Finished May 12 01:34:19 PM PDT 24
Peak memory 195264 kb
Host smart-71fc8bc4-fabd-4548-a9ee-10a1ad5862fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261988437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4261988437
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2497016496
Short name T342
Test name
Test status
Simulation time 4752217851 ps
CPU time 57.39 seconds
Started May 12 01:34:19 PM PDT 24
Finished May 12 01:35:17 PM PDT 24
Peak memory 227264 kb
Host smart-deae2b19-d3f9-4cd7-ab60-54b16a180b4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497016496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2497016496
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2138289040
Short name T427
Test name
Test status
Simulation time 2449802476 ps
CPU time 32.13 seconds
Started May 12 01:34:15 PM PDT 24
Finished May 12 01:34:47 PM PDT 24
Peak memory 200676 kb
Host smart-939cbcae-1994-4780-bb29-27f8d0780a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138289040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2138289040
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.705252969
Short name T273
Test name
Test status
Simulation time 3616009656 ps
CPU time 758.98 seconds
Started May 12 01:34:16 PM PDT 24
Finished May 12 01:46:56 PM PDT 24
Peak memory 678576 kb
Host smart-33b415d2-1eb9-4f54-af7b-16b776339fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705252969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.705252969
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1174248611
Short name T13
Test name
Test status
Simulation time 21712155940 ps
CPU time 28.18 seconds
Started May 12 01:34:15 PM PDT 24
Finished May 12 01:34:44 PM PDT 24
Peak memory 200672 kb
Host smart-e9b1604d-d4d4-42c4-ad5b-6e3ecd259391
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174248611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1174248611
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_smoke.1456941524
Short name T241
Test name
Test status
Simulation time 661963236 ps
CPU time 4.17 seconds
Started May 12 01:34:18 PM PDT 24
Finished May 12 01:34:22 PM PDT 24
Peak memory 200512 kb
Host smart-61201327-f55e-470d-aa54-3178ee9be2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456941524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1456941524
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1367846558
Short name T343
Test name
Test status
Simulation time 31099523 ps
CPU time 1.07 seconds
Started May 12 01:34:14 PM PDT 24
Finished May 12 01:34:15 PM PDT 24
Peak memory 200124 kb
Host smart-d2664859-3c71-4f31-bbae-a9c565ac4a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367846558 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1367846558
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.320798208
Short name T280
Test name
Test status
Simulation time 735161230259 ps
CPU time 478.06 seconds
Started May 12 01:34:19 PM PDT 24
Finished May 12 01:42:18 PM PDT 24
Peak memory 200632 kb
Host smart-45f849c2-1965-47cd-971d-1ad75f74beac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320798208 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.320798208
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4292696404
Short name T217
Test name
Test status
Simulation time 23634509 ps
CPU time 0.6 seconds
Started May 12 01:34:20 PM PDT 24
Finished May 12 01:34:21 PM PDT 24
Peak memory 196320 kb
Host smart-83623551-0891-4176-8d88-9ae7e35d90d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292696404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4292696404
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2322618296
Short name T400
Test name
Test status
Simulation time 359231129 ps
CPU time 12.4 seconds
Started May 12 01:34:22 PM PDT 24
Finished May 12 01:34:35 PM PDT 24
Peak memory 200636 kb
Host smart-6b626696-e7f9-4080-a2df-8d01e61da903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322618296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2322618296
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2093855116
Short name T193
Test name
Test status
Simulation time 11068168148 ps
CPU time 41.05 seconds
Started May 12 01:34:18 PM PDT 24
Finished May 12 01:35:00 PM PDT 24
Peak memory 200672 kb
Host smart-00637369-4131-49dd-b691-2559a6b02121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093855116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2093855116
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2379245915
Short name T75
Test name
Test status
Simulation time 8888248533 ps
CPU time 456.81 seconds
Started May 12 01:34:17 PM PDT 24
Finished May 12 01:41:54 PM PDT 24
Peak memory 685104 kb
Host smart-ff422ede-2173-4018-a67e-2058482ae102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379245915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2379245915
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2962932756
Short name T289
Test name
Test status
Simulation time 1307026168 ps
CPU time 75.77 seconds
Started May 12 01:34:18 PM PDT 24
Finished May 12 01:35:34 PM PDT 24
Peak memory 200588 kb
Host smart-560c982b-be6a-40d8-922d-62ded0e1b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962932756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2962932756
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3501960911
Short name T147
Test name
Test status
Simulation time 400004473 ps
CPU time 4.71 seconds
Started May 12 01:34:17 PM PDT 24
Finished May 12 01:34:22 PM PDT 24
Peak memory 200564 kb
Host smart-c33078ca-9c2c-49b3-90b7-78d37ed66c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501960911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3501960911
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1184759492
Short name T2
Test name
Test status
Simulation time 48007341 ps
CPU time 1.1 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:34:25 PM PDT 24
Peak memory 200420 kb
Host smart-3f36fb4a-a82d-4991-8518-faecec14de51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184759492 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1184759492
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1089362266
Short name T252
Test name
Test status
Simulation time 78521074248 ps
CPU time 481.37 seconds
Started May 12 01:34:19 PM PDT 24
Finished May 12 01:42:21 PM PDT 24
Peak memory 200652 kb
Host smart-8b0ae3c0-6158-4bbf-aed7-4c2f54ac9c14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089362266 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1089362266
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3437762833
Short name T251
Test name
Test status
Simulation time 64671689 ps
CPU time 0.59 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 196268 kb
Host smart-033cca83-fa18-4ca0-bd86-c7ab746c50af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437762833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3437762833
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2615650479
Short name T293
Test name
Test status
Simulation time 459144043 ps
CPU time 21.49 seconds
Started May 12 01:34:21 PM PDT 24
Finished May 12 01:34:42 PM PDT 24
Peak memory 208760 kb
Host smart-8fb6a678-64ab-47c4-a373-69481bde9eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615650479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2615650479
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3707375959
Short name T321
Test name
Test status
Simulation time 2182397008 ps
CPU time 28.4 seconds
Started May 12 01:34:22 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 200692 kb
Host smart-3e86d352-95c2-4b15-9a37-bbacd635d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707375959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3707375959
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1743481796
Short name T354
Test name
Test status
Simulation time 2209172316 ps
CPU time 524.9 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:43:09 PM PDT 24
Peak memory 680236 kb
Host smart-e441fd06-12e0-4740-881b-4569e5cd0057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743481796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1743481796
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3265619540
Short name T405
Test name
Test status
Simulation time 3839683316 ps
CPU time 16.96 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 200544 kb
Host smart-f554cef4-7124-43e3-bafc-7307110fd1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265619540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3265619540
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1566198214
Short name T344
Test name
Test status
Simulation time 556378824 ps
CPU time 5.3 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:34:29 PM PDT 24
Peak memory 200540 kb
Host smart-993ec0df-9182-44e7-83e1-6fae0c307d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566198214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1566198214
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3310704138
Short name T133
Test name
Test status
Simulation time 111288708 ps
CPU time 1.19 seconds
Started May 12 01:34:25 PM PDT 24
Finished May 12 01:34:27 PM PDT 24
Peak memory 200504 kb
Host smart-a551aad2-6bd2-4378-a419-03f40d41df6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310704138 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3310704138
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2451880031
Short name T124
Test name
Test status
Simulation time 40638915645 ps
CPU time 548.61 seconds
Started May 12 01:34:22 PM PDT 24
Finished May 12 01:43:31 PM PDT 24
Peak memory 200620 kb
Host smart-146e87e0-60bd-4e5b-aeef-46ceef7a4b63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451880031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2451880031
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2134928819
Short name T377
Test name
Test status
Simulation time 28919068 ps
CPU time 0.65 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:34:27 PM PDT 24
Peak memory 196300 kb
Host smart-defa2cef-9d8d-4102-a55f-d9783da0b44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134928819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2134928819
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4087690565
Short name T232
Test name
Test status
Simulation time 1150831253 ps
CPU time 19.36 seconds
Started May 12 01:34:24 PM PDT 24
Finished May 12 01:34:44 PM PDT 24
Peak memory 217000 kb
Host smart-a0b24bc1-2d00-4a45-9d51-52fcbda86730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087690565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4087690565
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2138879949
Short name T32
Test name
Test status
Simulation time 411019486 ps
CPU time 6.43 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:34:30 PM PDT 24
Peak memory 200440 kb
Host smart-7d624e22-8ce6-4133-8711-8f07e9b32a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138879949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2138879949
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4229782477
Short name T301
Test name
Test status
Simulation time 9832082416 ps
CPU time 599.16 seconds
Started May 12 01:34:24 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 516168 kb
Host smart-ff4d81a6-14e9-48a6-8c87-e9fdce866097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229782477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4229782477
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1753579743
Short name T382
Test name
Test status
Simulation time 1125858051 ps
CPU time 16.36 seconds
Started May 12 01:34:28 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200512 kb
Host smart-f58df3a4-a4f5-49f7-ba36-1a0251562fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753579743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1753579743
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.902337063
Short name T5
Test name
Test status
Simulation time 1715097418 ps
CPU time 6.34 seconds
Started May 12 01:34:23 PM PDT 24
Finished May 12 01:34:30 PM PDT 24
Peak memory 200552 kb
Host smart-f8964ca1-2812-4929-84c2-fe6f7c443d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902337063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.902337063
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4148532255
Short name T356
Test name
Test status
Simulation time 42998590039 ps
CPU time 1984.37 seconds
Started May 12 01:34:25 PM PDT 24
Finished May 12 02:07:30 PM PDT 24
Peak memory 769132 kb
Host smart-542c2a1a-47e4-49de-b173-749af6aa5b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148532255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4148532255
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.263917409
Short name T190
Test name
Test status
Simulation time 32703616 ps
CPU time 1.25 seconds
Started May 12 01:34:22 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 200596 kb
Host smart-97d2740c-7128-4f79-824e-8357b9400ff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263917409 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.263917409
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.542040795
Short name T174
Test name
Test status
Simulation time 64376165509 ps
CPU time 465.62 seconds
Started May 12 01:34:25 PM PDT 24
Finished May 12 01:42:11 PM PDT 24
Peak memory 200600 kb
Host smart-472994c1-5f2a-4983-be5d-ae88fedf5bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542040795 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.542040795
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1214708983
Short name T24
Test name
Test status
Simulation time 376728604 ps
CPU time 2.99 seconds
Started May 12 01:34:24 PM PDT 24
Finished May 12 01:34:28 PM PDT 24
Peak memory 200340 kb
Host smart-8963a155-3465-4a90-9fdd-55cb9ef3110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214708983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1214708983
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1405639946
Short name T419
Test name
Test status
Simulation time 21503974 ps
CPU time 0.6 seconds
Started May 12 01:34:27 PM PDT 24
Finished May 12 01:34:29 PM PDT 24
Peak memory 196300 kb
Host smart-c2f0b01d-df50-4648-81ab-05f6345f1dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405639946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1405639946
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.992884543
Short name T201
Test name
Test status
Simulation time 3353687767 ps
CPU time 41.05 seconds
Started May 12 01:34:28 PM PDT 24
Finished May 12 01:35:10 PM PDT 24
Peak memory 233408 kb
Host smart-783668aa-a3ae-4839-b545-7927fa4d383b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992884543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.992884543
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3463209364
Short name T369
Test name
Test status
Simulation time 4307788960 ps
CPU time 41.58 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:35:08 PM PDT 24
Peak memory 200760 kb
Host smart-828313b6-8e4f-478b-aa3f-41de9ccb6d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463209364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3463209364
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1780231155
Short name T238
Test name
Test status
Simulation time 5210286959 ps
CPU time 647.12 seconds
Started May 12 01:34:29 PM PDT 24
Finished May 12 01:45:16 PM PDT 24
Peak memory 758044 kb
Host smart-cca07ed6-3f68-4d14-ad96-a4a3e1c12e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780231155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1780231155
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2169538728
Short name T440
Test name
Test status
Simulation time 687083635 ps
CPU time 9.48 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:34:37 PM PDT 24
Peak memory 200604 kb
Host smart-7d71c4f5-1b66-4949-bae1-746fe9213750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169538728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2169538728
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1080128690
Short name T150
Test name
Test status
Simulation time 296396288 ps
CPU time 3.37 seconds
Started May 12 01:34:27 PM PDT 24
Finished May 12 01:34:31 PM PDT 24
Peak memory 200644 kb
Host smart-21cafb7c-956f-4277-828e-8318b267c18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080128690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1080128690
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2054664839
Short name T218
Test name
Test status
Simulation time 43046334 ps
CPU time 1.01 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:34:28 PM PDT 24
Peak memory 200228 kb
Host smart-6b007f90-8766-4272-a784-77d417fa2953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054664839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2054664839
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.4173902551
Short name T138
Test name
Test status
Simulation time 25849907199 ps
CPU time 481.45 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:42:28 PM PDT 24
Peak memory 200568 kb
Host smart-52350a3f-e470-404f-b118-8764515d945e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173902551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.4173902551
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.719294873
Short name T172
Test name
Test status
Simulation time 30239143 ps
CPU time 0.61 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:33:36 PM PDT 24
Peak memory 196236 kb
Host smart-da305363-2383-418c-8ce9-4d06028c16fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719294873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.719294873
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.131216757
Short name T117
Test name
Test status
Simulation time 955126649 ps
CPU time 22.6 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:33:55 PM PDT 24
Peak memory 208636 kb
Host smart-be8c8b3f-b061-4821-9512-f7db6c2e5a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131216757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.131216757
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2524637341
Short name T225
Test name
Test status
Simulation time 5632170581 ps
CPU time 27.01 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:34:00 PM PDT 24
Peak memory 200700 kb
Host smart-2921cb2f-3f8b-462b-aad4-720c445a0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524637341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2524637341
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4010622879
Short name T297
Test name
Test status
Simulation time 6044493655 ps
CPU time 459.77 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:41:12 PM PDT 24
Peak memory 686848 kb
Host smart-d9e89224-d29d-4488-bf0c-e30d27cae87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010622879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4010622879
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4256460576
Short name T271
Test name
Test status
Simulation time 3523826663 ps
CPU time 34.86 seconds
Started May 12 01:33:33 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 200596 kb
Host smart-5f3eac2b-ce0d-4350-82e3-cea484ec13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256460576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4256460576
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3508664932
Short name T28
Test name
Test status
Simulation time 880212897 ps
CPU time 1.46 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 219800 kb
Host smart-da5e9738-62da-4c60-87f7-d7db2ebce7de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508664932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3508664932
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3622640645
Short name T291
Test name
Test status
Simulation time 250191062 ps
CPU time 3.27 seconds
Started May 12 01:33:36 PM PDT 24
Finished May 12 01:33:40 PM PDT 24
Peak memory 200572 kb
Host smart-a15099f0-7fe9-4cca-a4da-bc7eb8a975ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622640645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3622640645
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1682379692
Short name T243
Test name
Test status
Simulation time 207370502 ps
CPU time 1.26 seconds
Started May 12 01:33:32 PM PDT 24
Finished May 12 01:33:33 PM PDT 24
Peak memory 200528 kb
Host smart-34c4bbdd-d86f-41b3-82e6-8a5b2569f62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682379692 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1682379692
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.587446827
Short name T331
Test name
Test status
Simulation time 25581537450 ps
CPU time 459.91 seconds
Started May 12 01:33:31 PM PDT 24
Finished May 12 01:41:12 PM PDT 24
Peak memory 200632 kb
Host smart-c4c43131-79b9-4ef2-845a-6a08c171304b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587446827 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.587446827
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1956832853
Short name T213
Test name
Test status
Simulation time 45546517 ps
CPU time 0.56 seconds
Started May 12 01:34:30 PM PDT 24
Finished May 12 01:34:31 PM PDT 24
Peak memory 195992 kb
Host smart-63facbf6-cecd-4a8f-be7d-6d5b2f215ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956832853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1956832853
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4127245733
Short name T186
Test name
Test status
Simulation time 3640398716 ps
CPU time 48.69 seconds
Started May 12 01:34:25 PM PDT 24
Finished May 12 01:35:14 PM PDT 24
Peak memory 217384 kb
Host smart-0021445b-44af-4d50-a292-a94ff0f8c5d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127245733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4127245733
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1563519741
Short name T367
Test name
Test status
Simulation time 3304053585 ps
CPU time 32.68 seconds
Started May 12 01:34:29 PM PDT 24
Finished May 12 01:35:02 PM PDT 24
Peak memory 200924 kb
Host smart-7a62e0fa-ae95-4ab3-a58a-cfef3fbb3ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563519741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1563519741
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2607141333
Short name T441
Test name
Test status
Simulation time 3442520682 ps
CPU time 686.44 seconds
Started May 12 01:34:34 PM PDT 24
Finished May 12 01:46:01 PM PDT 24
Peak memory 721896 kb
Host smart-1649f18e-2ddd-4239-abdf-34381c8ee2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607141333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2607141333
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3026896751
Short name T53
Test name
Test status
Simulation time 5708332521 ps
CPU time 51.41 seconds
Started May 12 01:34:27 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 200972 kb
Host smart-43033cd6-3a33-4975-a9a7-fd8e8bf3be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026896751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3026896751
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2691816032
Short name T399
Test name
Test status
Simulation time 426412884 ps
CPU time 6.49 seconds
Started May 12 01:34:26 PM PDT 24
Finished May 12 01:34:33 PM PDT 24
Peak memory 200532 kb
Host smart-d0efb71f-f1b9-495c-afce-aafbd4b6228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691816032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2691816032
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4229573455
Short name T42
Test name
Test status
Simulation time 30130791 ps
CPU time 1.17 seconds
Started May 12 01:34:36 PM PDT 24
Finished May 12 01:34:38 PM PDT 24
Peak memory 200524 kb
Host smart-c6a39546-2ddd-4d30-879c-8b01c4d27fd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229573455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4229573455
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.349622358
Short name T315
Test name
Test status
Simulation time 40922022379 ps
CPU time 524.15 seconds
Started May 12 01:34:31 PM PDT 24
Finished May 12 01:43:16 PM PDT 24
Peak memory 200612 kb
Host smart-c574cbbf-88d7-49bb-b73d-4a6bb7e15e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349622358 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.349622358
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.765570978
Short name T259
Test name
Test status
Simulation time 11965696 ps
CPU time 0.59 seconds
Started May 12 01:34:33 PM PDT 24
Finished May 12 01:34:34 PM PDT 24
Peak memory 195244 kb
Host smart-bfaf227c-bd2d-41b1-86db-0aeea04bae8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765570978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.765570978
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2159319020
Short name T49
Test name
Test status
Simulation time 3061369827 ps
CPU time 25.97 seconds
Started May 12 01:34:34 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 200640 kb
Host smart-5cb436ff-da45-4352-8d43-53435196f064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159319020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2159319020
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1345579410
Short name T430
Test name
Test status
Simulation time 3270027341 ps
CPU time 44.52 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:35:23 PM PDT 24
Peak memory 200516 kb
Host smart-c9eca37d-1930-4d16-9792-774fa44d3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345579410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1345579410
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.794200255
Short name T205
Test name
Test status
Simulation time 25019754933 ps
CPU time 859.49 seconds
Started May 12 01:34:33 PM PDT 24
Finished May 12 01:48:53 PM PDT 24
Peak memory 560100 kb
Host smart-24e6db72-1b57-4fba-8567-ed01f85c2f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794200255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.794200255
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3089009862
Short name T435
Test name
Test status
Simulation time 5945148768 ps
CPU time 110.09 seconds
Started May 12 01:34:27 PM PDT 24
Finished May 12 01:36:18 PM PDT 24
Peak memory 200588 kb
Host smart-3a6d197e-5e77-4c2a-8362-c0d8ea13a26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089009862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3089009862
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.45024178
Short name T160
Test name
Test status
Simulation time 134341989 ps
CPU time 2.37 seconds
Started May 12 01:34:30 PM PDT 24
Finished May 12 01:34:33 PM PDT 24
Peak memory 200644 kb
Host smart-b33c6eae-6b1c-427b-8ead-c0726d0bf354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45024178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.45024178
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1345004452
Short name T70
Test name
Test status
Simulation time 278202770429 ps
CPU time 1881.09 seconds
Started May 12 01:34:34 PM PDT 24
Finished May 12 02:05:56 PM PDT 24
Peak memory 670388 kb
Host smart-2dae0971-b476-4016-90d9-b60505321c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345004452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1345004452
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.903544476
Short name T194
Test name
Test status
Simulation time 66663623 ps
CPU time 1.35 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:39 PM PDT 24
Peak memory 200512 kb
Host smart-76246b4f-439b-4efa-9b02-7b04269dd9e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903544476 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.903544476
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2410447738
Short name T258
Test name
Test status
Simulation time 139059168671 ps
CPU time 467.3 seconds
Started May 12 01:34:35 PM PDT 24
Finished May 12 01:42:23 PM PDT 24
Peak memory 200684 kb
Host smart-523b8d7e-428b-4327-a32d-da2c127a939f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410447738 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2410447738
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3393771813
Short name T261
Test name
Test status
Simulation time 13063620 ps
CPU time 0.59 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:38 PM PDT 24
Peak memory 197048 kb
Host smart-7428a3c1-28f9-4a31-8371-b0d62a49e6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393771813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3393771813
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1513644374
Short name T7
Test name
Test status
Simulation time 4092369271 ps
CPU time 48.43 seconds
Started May 12 01:34:34 PM PDT 24
Finished May 12 01:35:23 PM PDT 24
Peak memory 224380 kb
Host smart-9695d96c-85fd-484c-869e-82c021f9d935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513644374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1513644374
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.873857129
Short name T298
Test name
Test status
Simulation time 1518411854 ps
CPU time 28.44 seconds
Started May 12 01:34:32 PM PDT 24
Finished May 12 01:35:00 PM PDT 24
Peak memory 200524 kb
Host smart-afa3ee46-885b-4241-86ba-4460e85cf0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873857129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.873857129
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.500200674
Short name T188
Test name
Test status
Simulation time 5616261475 ps
CPU time 222.67 seconds
Started May 12 01:34:33 PM PDT 24
Finished May 12 01:38:16 PM PDT 24
Peak memory 600668 kb
Host smart-2e0364d6-0bee-4810-a731-394aaebac707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500200674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.500200674
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3222640949
Short name T436
Test name
Test status
Simulation time 908011602 ps
CPU time 9.39 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:47 PM PDT 24
Peak memory 200256 kb
Host smart-ab765b1c-72c6-43c4-8aeb-72ea3a31b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222640949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3222640949
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.341016117
Short name T461
Test name
Test status
Simulation time 1091642972 ps
CPU time 7.32 seconds
Started May 12 01:34:31 PM PDT 24
Finished May 12 01:34:39 PM PDT 24
Peak memory 200636 kb
Host smart-e9d7fbf7-f699-46f9-a537-c36cc1dfc929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341016117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.341016117
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3400518813
Short name T439
Test name
Test status
Simulation time 55698027 ps
CPU time 1.23 seconds
Started May 12 01:34:33 PM PDT 24
Finished May 12 01:34:35 PM PDT 24
Peak memory 200624 kb
Host smart-292c475f-8c79-4569-8843-e00d288f2167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400518813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3400518813
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1911750888
Short name T178
Test name
Test status
Simulation time 43057224023 ps
CPU time 534.77 seconds
Started May 12 01:34:33 PM PDT 24
Finished May 12 01:43:28 PM PDT 24
Peak memory 200672 kb
Host smart-5ecfe184-651c-4b4c-8014-d26f417560e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911750888 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1911750888
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3974538656
Short name T339
Test name
Test status
Simulation time 110019268 ps
CPU time 0.57 seconds
Started May 12 01:34:44 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 196024 kb
Host smart-7ba4315f-94a0-4973-aee7-9252fa836d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974538656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3974538656
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3639914961
Short name T137
Test name
Test status
Simulation time 1011192099 ps
CPU time 60.32 seconds
Started May 12 01:34:35 PM PDT 24
Finished May 12 01:35:36 PM PDT 24
Peak memory 230220 kb
Host smart-033d7062-95d4-4b8d-8eb6-2bb09694e057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639914961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3639914961
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.189862639
Short name T102
Test name
Test status
Simulation time 3868913410 ps
CPU time 19.11 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:57 PM PDT 24
Peak memory 200592 kb
Host smart-b2ceca93-d26a-4be1-9aba-ed7d25136161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189862639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.189862639
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.213168101
Short name T351
Test name
Test status
Simulation time 16641146842 ps
CPU time 986.97 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:51:04 PM PDT 24
Peak memory 762312 kb
Host smart-07fdb99c-3995-4640-864e-047b7c0508da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213168101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.213168101
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3937674658
Short name T63
Test name
Test status
Simulation time 213809668 ps
CPU time 13.25 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:51 PM PDT 24
Peak memory 200392 kb
Host smart-418aa6f0-e826-4c72-bdb4-308128b12f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937674658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3937674658
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.275861698
Short name T368
Test name
Test status
Simulation time 22865847 ps
CPU time 0.78 seconds
Started May 12 01:34:36 PM PDT 24
Finished May 12 01:34:38 PM PDT 24
Peak memory 197864 kb
Host smart-9ffdb627-763e-4a3f-822d-23796df67be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275861698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.275861698
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2216471473
Short name T41
Test name
Test status
Simulation time 97743171 ps
CPU time 0.93 seconds
Started May 12 01:34:43 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 199156 kb
Host smart-2776f4c6-1866-4880-b4be-e2fb3c7c8f86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216471473 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2216471473
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2037178490
Short name T332
Test name
Test status
Simulation time 88546851779 ps
CPU time 539.77 seconds
Started May 12 01:34:38 PM PDT 24
Finished May 12 01:43:38 PM PDT 24
Peak memory 200608 kb
Host smart-02df10ff-4713-48c0-91c1-aa7af90e1551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037178490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2037178490
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1074576784
Short name T432
Test name
Test status
Simulation time 12557590 ps
CPU time 0.58 seconds
Started May 12 01:34:40 PM PDT 24
Finished May 12 01:34:41 PM PDT 24
Peak memory 196224 kb
Host smart-bfd696c1-c0e6-4378-aa14-5846cf7edf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074576784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1074576784
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3432117493
Short name T307
Test name
Test status
Simulation time 12780634346 ps
CPU time 64.63 seconds
Started May 12 01:34:40 PM PDT 24
Finished May 12 01:35:45 PM PDT 24
Peak memory 233468 kb
Host smart-c9fce951-0c26-4726-8d3e-31b124fed180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432117493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3432117493
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.922592361
Short name T195
Test name
Test status
Simulation time 2426929068 ps
CPU time 49.65 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:35:27 PM PDT 24
Peak memory 200748 kb
Host smart-4175409c-df6f-4f0f-b3c1-21efebf8e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922592361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.922592361
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1214251248
Short name T149
Test name
Test status
Simulation time 681436997 ps
CPU time 128.63 seconds
Started May 12 01:34:44 PM PDT 24
Finished May 12 01:36:53 PM PDT 24
Peak memory 453924 kb
Host smart-b814f0cc-40f9-492c-9f4a-e2f93d126219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214251248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1214251248
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.556345501
Short name T253
Test name
Test status
Simulation time 3923995260 ps
CPU time 42.57 seconds
Started May 12 01:34:36 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 200764 kb
Host smart-9233827d-b743-412e-9577-4856b2e1918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556345501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.556345501
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3605319817
Short name T187
Test name
Test status
Simulation time 1357297573 ps
CPU time 5.5 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 200564 kb
Host smart-d73a2b6c-2c52-4041-bab4-89cd165b3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605319817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3605319817
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3129926555
Short name T204
Test name
Test status
Simulation time 97767416 ps
CPU time 1.01 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:34:42 PM PDT 24
Peak memory 200120 kb
Host smart-a78bdc64-a598-4ae5-8336-971e8611a354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129926555 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3129926555
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2900130512
Short name T442
Test name
Test status
Simulation time 75515328684 ps
CPU time 536.9 seconds
Started May 12 01:34:37 PM PDT 24
Finished May 12 01:43:35 PM PDT 24
Peak memory 200608 kb
Host smart-3f04d40d-ee9d-494b-8ceb-c3590819175a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900130512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2900130512
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1644029171
Short name T476
Test name
Test status
Simulation time 37381446 ps
CPU time 0.56 seconds
Started May 12 01:34:42 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 195916 kb
Host smart-c4464a50-140d-42c6-adef-3035f36643c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644029171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1644029171
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2768627036
Short name T158
Test name
Test status
Simulation time 567770525 ps
CPU time 15.47 seconds
Started May 12 01:34:42 PM PDT 24
Finished May 12 01:34:58 PM PDT 24
Peak memory 233524 kb
Host smart-094fd1ea-2720-4aaa-bf16-9eb473224fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768627036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2768627036
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.427672840
Short name T391
Test name
Test status
Simulation time 1592963420 ps
CPU time 17 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:34:58 PM PDT 24
Peak memory 200616 kb
Host smart-a06442d2-60a1-4eb3-86df-b2f11963a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427672840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.427672840
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2184574595
Short name T304
Test name
Test status
Simulation time 8105524334 ps
CPU time 693.31 seconds
Started May 12 01:34:40 PM PDT 24
Finished May 12 01:46:14 PM PDT 24
Peak memory 743848 kb
Host smart-86c916c4-00b0-4130-9ec5-25dca65b3555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184574595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2184574595
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2634707541
Short name T196
Test name
Test status
Simulation time 632826373 ps
CPU time 37.4 seconds
Started May 12 01:34:40 PM PDT 24
Finished May 12 01:35:18 PM PDT 24
Peak memory 200564 kb
Host smart-05958b15-16b9-4219-9969-8816a1e6dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634707541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2634707541
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3049999668
Short name T177
Test name
Test status
Simulation time 592003413 ps
CPU time 2.1 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 200564 kb
Host smart-7dbad6e2-2617-4b0f-afba-239310d268ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049999668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3049999668
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3144685369
Short name T39
Test name
Test status
Simulation time 340930697 ps
CPU time 1.63 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 200544 kb
Host smart-c118c330-3248-4c69-8cf6-ef61a94c2b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144685369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3144685369
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.795761599
Short name T295
Test name
Test status
Simulation time 35435187 ps
CPU time 1.25 seconds
Started May 12 01:34:43 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200488 kb
Host smart-242a3172-d56e-45e1-b2de-983aa77f5e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795761599 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.795761599
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3751783338
Short name T284
Test name
Test status
Simulation time 106086719937 ps
CPU time 466.53 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:42:28 PM PDT 24
Peak memory 200624 kb
Host smart-00b90d73-17dc-4e6c-ad5c-0de19f011963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751783338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3751783338
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3341038816
Short name T235
Test name
Test status
Simulation time 44386881 ps
CPU time 0.57 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:34:49 PM PDT 24
Peak memory 195880 kb
Host smart-ac06a9c8-81dd-47a2-8429-4351928738e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341038816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3341038816
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1956386634
Short name T47
Test name
Test status
Simulation time 2049076341 ps
CPU time 25.09 seconds
Started May 12 01:34:41 PM PDT 24
Finished May 12 01:35:07 PM PDT 24
Peak memory 200632 kb
Host smart-b62038f8-f77c-4ed1-acd4-9972f9ceca8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956386634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1956386634
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3313199169
Short name T378
Test name
Test status
Simulation time 632501378 ps
CPU time 33.97 seconds
Started May 12 01:34:43 PM PDT 24
Finished May 12 01:35:18 PM PDT 24
Peak memory 200556 kb
Host smart-fe99674a-944f-4e5e-8f94-2671888f7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313199169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3313199169
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1168825339
Short name T154
Test name
Test status
Simulation time 12379303091 ps
CPU time 777.48 seconds
Started May 12 01:34:45 PM PDT 24
Finished May 12 01:47:43 PM PDT 24
Peak memory 735364 kb
Host smart-20f645ff-00ed-468e-b44a-878ffc4e7871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168825339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1168825339
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1973390907
Short name T425
Test name
Test status
Simulation time 1627574290 ps
CPU time 93.92 seconds
Started May 12 01:34:42 PM PDT 24
Finished May 12 01:36:16 PM PDT 24
Peak memory 200736 kb
Host smart-6888c4a6-5e61-4291-a91b-8c15928e0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973390907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1973390907
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.428670472
Short name T257
Test name
Test status
Simulation time 32141630 ps
CPU time 0.81 seconds
Started May 12 01:34:40 PM PDT 24
Finished May 12 01:34:41 PM PDT 24
Peak memory 198576 kb
Host smart-583784f2-2b4b-4d7a-a794-b036539a0ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428670472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.428670472
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3611632748
Short name T366
Test name
Test status
Simulation time 74149242 ps
CPU time 1.31 seconds
Started May 12 01:34:44 PM PDT 24
Finished May 12 01:34:46 PM PDT 24
Peak memory 200552 kb
Host smart-4db92e34-8772-44e9-a29d-48f353e41a0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611632748 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3611632748
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1145352495
Short name T6
Test name
Test status
Simulation time 24429887728 ps
CPU time 446.81 seconds
Started May 12 01:34:45 PM PDT 24
Finished May 12 01:42:13 PM PDT 24
Peak memory 200536 kb
Host smart-1cddc2d3-10f7-4fd9-824d-61c345eb45a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145352495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1145352495
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3260099827
Short name T276
Test name
Test status
Simulation time 56634584 ps
CPU time 0.66 seconds
Started May 12 01:34:47 PM PDT 24
Finished May 12 01:34:48 PM PDT 24
Peak memory 196300 kb
Host smart-3d5595e6-96bb-4b3a-839a-cf77e4be2ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260099827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3260099827
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1010861595
Short name T299
Test name
Test status
Simulation time 1531560798 ps
CPU time 21.34 seconds
Started May 12 01:34:44 PM PDT 24
Finished May 12 01:35:07 PM PDT 24
Peak memory 206432 kb
Host smart-0620d443-44e0-468d-8857-d83baf9d053e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010861595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1010861595
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2420046000
Short name T266
Test name
Test status
Simulation time 3555464404 ps
CPU time 50.24 seconds
Started May 12 01:34:45 PM PDT 24
Finished May 12 01:35:36 PM PDT 24
Peak memory 200704 kb
Host smart-ad31bd7b-941d-4924-837d-2a432388d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420046000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2420046000
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2066870116
Short name T54
Test name
Test status
Simulation time 3271012277 ps
CPU time 759.9 seconds
Started May 12 01:34:44 PM PDT 24
Finished May 12 01:47:25 PM PDT 24
Peak memory 666452 kb
Host smart-f5a04686-de90-4a34-9843-21d9f1ee7c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066870116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2066870116
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3591554026
Short name T371
Test name
Test status
Simulation time 4487871808 ps
CPU time 62.32 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:35:51 PM PDT 24
Peak memory 200632 kb
Host smart-db6fbb1f-6b06-442d-8670-0000d2258ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591554026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3591554026
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.476212523
Short name T370
Test name
Test status
Simulation time 171011613 ps
CPU time 2.84 seconds
Started May 12 01:34:43 PM PDT 24
Finished May 12 01:34:46 PM PDT 24
Peak memory 200580 kb
Host smart-184a9021-927f-4fe4-8fbf-203504988831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476212523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.476212523
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.4158763045
Short name T66
Test name
Test status
Simulation time 60489437 ps
CPU time 1.23 seconds
Started May 12 01:34:43 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200264 kb
Host smart-00fd3a11-7d90-42d0-a8de-697c8d9acfd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158763045 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.4158763045
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.4275536686
Short name T437
Test name
Test status
Simulation time 9437134656 ps
CPU time 451.92 seconds
Started May 12 01:34:49 PM PDT 24
Finished May 12 01:42:22 PM PDT 24
Peak memory 200576 kb
Host smart-5c69fefe-f5f5-4743-942f-7ef954584ff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275536686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.4275536686
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2287299185
Short name T122
Test name
Test status
Simulation time 13037568 ps
CPU time 0.58 seconds
Started May 12 01:34:49 PM PDT 24
Finished May 12 01:34:50 PM PDT 24
Peak memory 197044 kb
Host smart-882204e8-c645-403c-a718-eafc247fac69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287299185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2287299185
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4056077607
Short name T33
Test name
Test status
Simulation time 556730195 ps
CPU time 26.12 seconds
Started May 12 01:34:49 PM PDT 24
Finished May 12 01:35:16 PM PDT 24
Peak memory 200452 kb
Host smart-d84b9e4d-5992-4334-9684-a651fb830509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056077607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4056077607
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3797750924
Short name T185
Test name
Test status
Simulation time 2726458379 ps
CPU time 27.86 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:35:17 PM PDT 24
Peak memory 200692 kb
Host smart-9ac336d1-ce73-424f-a438-33da4b55e4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797750924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3797750924
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4181195709
Short name T264
Test name
Test status
Simulation time 9513755451 ps
CPU time 1293.82 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:56:23 PM PDT 24
Peak memory 771608 kb
Host smart-97c19b8c-59e3-4872-b83d-36822b603ba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181195709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4181195709
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1797558629
Short name T162
Test name
Test status
Simulation time 2002457117 ps
CPU time 17.07 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:35:09 PM PDT 24
Peak memory 200516 kb
Host smart-1a34ac7a-1746-48e1-802f-2ceff11192b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797558629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1797558629
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3994193423
Short name T127
Test name
Test status
Simulation time 378966633 ps
CPU time 3.17 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 200568 kb
Host smart-566ed648-4a71-4dea-89ea-339af6daf601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994193423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3994193423
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3931606015
Short name T453
Test name
Test status
Simulation time 275990981 ps
CPU time 1.13 seconds
Started May 12 01:34:47 PM PDT 24
Finished May 12 01:34:49 PM PDT 24
Peak memory 200568 kb
Host smart-f6d2df2c-f7cd-479f-9094-afd6d257ef63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931606015 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3931606015
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1872812748
Short name T141
Test name
Test status
Simulation time 29527285101 ps
CPU time 510.67 seconds
Started May 12 01:34:47 PM PDT 24
Finished May 12 01:43:18 PM PDT 24
Peak memory 200672 kb
Host smart-42609370-6988-4d4c-a2cd-e8968235c214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872812748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1872812748
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.936544337
Short name T245
Test name
Test status
Simulation time 25562231 ps
CPU time 0.63 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 196336 kb
Host smart-4a87ea69-6c37-4ffb-aa0b-1d4cc5d679a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936544337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.936544337
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1522957369
Short name T329
Test name
Test status
Simulation time 460323018 ps
CPU time 25.47 seconds
Started May 12 01:34:46 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 227268 kb
Host smart-90558a4a-dc44-40cd-aadc-3cdb992fd19f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522957369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1522957369
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.671364661
Short name T274
Test name
Test status
Simulation time 429383751 ps
CPU time 24.14 seconds
Started May 12 01:34:50 PM PDT 24
Finished May 12 01:35:15 PM PDT 24
Peak memory 200580 kb
Host smart-2caf905c-aec5-48d8-9f78-4d0302a168df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671364661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.671364661
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_long_msg.219729156
Short name T248
Test name
Test status
Simulation time 3253207760 ps
CPU time 104.02 seconds
Started May 12 01:34:48 PM PDT 24
Finished May 12 01:36:33 PM PDT 24
Peak memory 200564 kb
Host smart-92479f87-0c14-4c8e-8811-bae748a1f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219729156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.219729156
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2545346650
Short name T302
Test name
Test status
Simulation time 854314949 ps
CPU time 5.47 seconds
Started May 12 01:34:47 PM PDT 24
Finished May 12 01:34:53 PM PDT 24
Peak memory 200600 kb
Host smart-3b9c1ab3-2135-4fc1-be0b-3372ff5e393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545346650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2545346650
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3746904362
Short name T164
Test name
Test status
Simulation time 173457347 ps
CPU time 1.27 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:34:56 PM PDT 24
Peak memory 200612 kb
Host smart-db00ce33-9f39-4880-a8b5-6366bfbf5397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746904362 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3746904362
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.831858697
Short name T65
Test name
Test status
Simulation time 8167035047 ps
CPU time 443.61 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:42:15 PM PDT 24
Peak memory 200860 kb
Host smart-4bec2da2-f8cc-42e1-ac22-bed4ea55cca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831858697 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.831858697
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2085616289
Short name T322
Test name
Test status
Simulation time 12743095 ps
CPU time 0.59 seconds
Started May 12 01:33:37 PM PDT 24
Finished May 12 01:33:38 PM PDT 24
Peak memory 195212 kb
Host smart-01bc8489-2a8c-435b-b388-a21e7ceac7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085616289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2085616289
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2618356952
Short name T120
Test name
Test status
Simulation time 2029901492 ps
CPU time 58.66 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:34:34 PM PDT 24
Peak memory 233148 kb
Host smart-e055d18e-01d8-4aa5-8db1-2f80f6dac7c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618356952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2618356952
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2824734163
Short name T326
Test name
Test status
Simulation time 27487172720 ps
CPU time 47.3 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 200716 kb
Host smart-e343b64a-a832-4cfd-a172-dcb36ddd7ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824734163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2824734163
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1709423131
Short name T374
Test name
Test status
Simulation time 499180602 ps
CPU time 120.47 seconds
Started May 12 01:33:38 PM PDT 24
Finished May 12 01:35:39 PM PDT 24
Peak memory 469188 kb
Host smart-bf65fa1d-c623-43da-93e5-82fe0c3cafca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709423131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1709423131
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1865191086
Short name T203
Test name
Test status
Simulation time 4630585976 ps
CPU time 92.96 seconds
Started May 12 01:33:33 PM PDT 24
Finished May 12 01:35:07 PM PDT 24
Peak memory 200720 kb
Host smart-3aa5a49e-e023-4666-be5f-bac5a372bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865191086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1865191086
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.747336315
Short name T30
Test name
Test status
Simulation time 67731323 ps
CPU time 0.82 seconds
Started May 12 01:33:36 PM PDT 24
Finished May 12 01:33:37 PM PDT 24
Peak memory 218876 kb
Host smart-c7a40e5b-2c94-40c6-bc25-990722267ce2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747336315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.747336315
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1026311844
Short name T169
Test name
Test status
Simulation time 224672802 ps
CPU time 1.86 seconds
Started May 12 01:33:33 PM PDT 24
Finished May 12 01:33:36 PM PDT 24
Peak memory 200512 kb
Host smart-68fa79e9-fe96-4ea2-9c5e-4e4315a61368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026311844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1026311844
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1582144738
Short name T265
Test name
Test status
Simulation time 82319734009 ps
CPU time 1620.43 seconds
Started May 12 01:33:34 PM PDT 24
Finished May 12 02:00:35 PM PDT 24
Peak memory 230396 kb
Host smart-53046441-ca9c-4b1a-85dc-d00dd3a31d85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582144738 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1582144738
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4187414518
Short name T38
Test name
Test status
Simulation time 57090604 ps
CPU time 1.31 seconds
Started May 12 01:33:38 PM PDT 24
Finished May 12 01:33:40 PM PDT 24
Peak memory 200488 kb
Host smart-ed38af60-aaab-4769-8f8c-f9dc44850175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187414518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4187414518
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.949171108
Short name T353
Test name
Test status
Simulation time 14932809972 ps
CPU time 409.45 seconds
Started May 12 01:33:37 PM PDT 24
Finished May 12 01:40:27 PM PDT 24
Peak memory 200652 kb
Host smart-e2ade81d-ca6f-4ad2-8a8a-3d6ae2935d9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949171108 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.949171108
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3547306250
Short name T308
Test name
Test status
Simulation time 14478941 ps
CPU time 0.59 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:34:56 PM PDT 24
Peak memory 197044 kb
Host smart-c1c5f004-d94d-4227-b61e-21531aa33641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547306250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3547306250
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2661391653
Short name T44
Test name
Test status
Simulation time 634413415 ps
CPU time 35.55 seconds
Started May 12 01:34:52 PM PDT 24
Finished May 12 01:35:28 PM PDT 24
Peak memory 222120 kb
Host smart-c3490d7f-8962-4fe2-9118-1cbb5d415b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661391653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2661391653
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3424220751
Short name T67
Test name
Test status
Simulation time 843708366 ps
CPU time 4.49 seconds
Started May 12 01:34:59 PM PDT 24
Finished May 12 01:35:04 PM PDT 24
Peak memory 200556 kb
Host smart-937b8f5e-7d0a-409e-96f0-5873dd6d30b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424220751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3424220751
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3425434114
Short name T362
Test name
Test status
Simulation time 2581112464 ps
CPU time 582.47 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:44:38 PM PDT 24
Peak memory 628292 kb
Host smart-bec77e03-481c-49ec-9928-27745709cc28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425434114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3425434114
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2775395568
Short name T43
Test name
Test status
Simulation time 760807589 ps
CPU time 10.33 seconds
Started May 12 01:34:56 PM PDT 24
Finished May 12 01:35:07 PM PDT 24
Peak memory 200388 kb
Host smart-bcebbfd8-2efb-4865-a21d-210442f7dddc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775395568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2775395568
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3212248585
Short name T272
Test name
Test status
Simulation time 1535891061 ps
CPU time 19.6 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:35:11 PM PDT 24
Peak memory 200592 kb
Host smart-67cfb933-4816-4304-b6c8-2df12b910891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212248585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3212248585
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1807635146
Short name T222
Test name
Test status
Simulation time 1619934999 ps
CPU time 5.85 seconds
Started May 12 01:34:51 PM PDT 24
Finished May 12 01:34:58 PM PDT 24
Peak memory 200548 kb
Host smart-cf93ec3e-7970-4482-af9e-cdcbc3c6a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807635146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1807635146
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1738694453
Short name T341
Test name
Test status
Simulation time 150355799 ps
CPU time 0.98 seconds
Started May 12 01:34:56 PM PDT 24
Finished May 12 01:34:58 PM PDT 24
Peak memory 199084 kb
Host smart-e5967566-02cf-438c-90b1-27d1b64c8b61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738694453 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1738694453
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3471351665
Short name T236
Test name
Test status
Simulation time 54359867744 ps
CPU time 453.35 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:42:29 PM PDT 24
Peak memory 200672 kb
Host smart-2a6dac1a-0999-4663-a5fd-ad156c91fecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471351665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3471351665
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.455443835
Short name T387
Test name
Test status
Simulation time 14066331 ps
CPU time 0.61 seconds
Started May 12 01:35:00 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 196204 kb
Host smart-81608fad-20fd-44d0-879e-36ffb7ce89f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455443835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.455443835
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.87394611
Short name T176
Test name
Test status
Simulation time 851656092 ps
CPU time 23.54 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 216880 kb
Host smart-f53e4960-5644-4ae1-ab28-25b82b7e2085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87394611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.87394611
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3887601326
Short name T408
Test name
Test status
Simulation time 2655693615 ps
CPU time 37.64 seconds
Started May 12 01:34:55 PM PDT 24
Finished May 12 01:35:33 PM PDT 24
Peak memory 200720 kb
Host smart-4f6f993e-fff6-4b1e-aef3-16e7e0fc6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887601326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3887601326
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2726143232
Short name T449
Test name
Test status
Simulation time 4000599736 ps
CPU time 289.14 seconds
Started May 12 01:34:59 PM PDT 24
Finished May 12 01:39:49 PM PDT 24
Peak memory 646828 kb
Host smart-92b128d2-9830-4edc-a59d-0a482d265e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726143232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2726143232
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.784983827
Short name T37
Test name
Test status
Simulation time 7820766211 ps
CPU time 84.46 seconds
Started May 12 01:34:57 PM PDT 24
Finished May 12 01:36:22 PM PDT 24
Peak memory 200736 kb
Host smart-7e89e6ce-7845-4949-8162-f37962f68f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784983827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.784983827
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.135882287
Short name T165
Test name
Test status
Simulation time 361290867 ps
CPU time 5.8 seconds
Started May 12 01:34:58 PM PDT 24
Finished May 12 01:35:04 PM PDT 24
Peak memory 200544 kb
Host smart-9a24fe1d-f23b-4db7-a235-d9ab3636d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135882287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.135882287
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1507141374
Short name T390
Test name
Test status
Simulation time 46522117 ps
CPU time 1.07 seconds
Started May 12 01:34:59 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 199412 kb
Host smart-b9b8d983-aea8-474f-b212-4cd3dc71275e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507141374 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1507141374
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3350647998
Short name T451
Test name
Test status
Simulation time 27954109535 ps
CPU time 440.92 seconds
Started May 12 01:34:59 PM PDT 24
Finished May 12 01:42:21 PM PDT 24
Peak memory 200080 kb
Host smart-2cda11eb-bf25-4aa1-9218-4093dba5a7d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350647998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3350647998
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1080025655
Short name T250
Test name
Test status
Simulation time 14702664 ps
CPU time 0.62 seconds
Started May 12 01:35:02 PM PDT 24
Finished May 12 01:35:03 PM PDT 24
Peak memory 195300 kb
Host smart-a5b1cde8-1db1-402b-b07d-b39aa210ec16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080025655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1080025655
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1020505921
Short name T45
Test name
Test status
Simulation time 582614505 ps
CPU time 30.08 seconds
Started May 12 01:34:59 PM PDT 24
Finished May 12 01:35:29 PM PDT 24
Peak memory 200516 kb
Host smart-fa42ea24-8fe5-4820-a011-b77e48ed687e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020505921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1020505921
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1325799023
Short name T327
Test name
Test status
Simulation time 3125217358 ps
CPU time 41.39 seconds
Started May 12 01:35:01 PM PDT 24
Finished May 12 01:35:43 PM PDT 24
Peak memory 200648 kb
Host smart-2e7b06d9-a4dd-477e-91e0-c0df29803327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325799023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1325799023
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1589584488
Short name T255
Test name
Test status
Simulation time 838740507 ps
CPU time 234.38 seconds
Started May 12 01:35:01 PM PDT 24
Finished May 12 01:38:56 PM PDT 24
Peak memory 645800 kb
Host smart-133c3585-6a7d-4655-b10b-a02732b0560f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589584488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1589584488
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2397279041
Short name T410
Test name
Test status
Simulation time 10640916779 ps
CPU time 40.2 seconds
Started May 12 01:35:00 PM PDT 24
Finished May 12 01:35:41 PM PDT 24
Peak memory 200696 kb
Host smart-661fdcb0-8267-4749-91ef-9124cca66593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397279041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2397279041
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2462441437
Short name T416
Test name
Test status
Simulation time 1286989190 ps
CPU time 4.32 seconds
Started May 12 01:35:01 PM PDT 24
Finished May 12 01:35:05 PM PDT 24
Peak memory 200588 kb
Host smart-faf94804-75ce-4d57-8f6f-b7d23ef3a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462441437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2462441437
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1825841205
Short name T309
Test name
Test status
Simulation time 40901583159 ps
CPU time 725.25 seconds
Started May 12 01:35:07 PM PDT 24
Finished May 12 01:47:13 PM PDT 24
Peak memory 233140 kb
Host smart-b96dc9ae-1943-4477-909f-42e142c28fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825841205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1825841205
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1600211413
Short name T317
Test name
Test status
Simulation time 71977026 ps
CPU time 1.45 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:13 PM PDT 24
Peak memory 200620 kb
Host smart-be4449ad-a044-4765-9e28-e1bebf081cd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600211413 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1600211413
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2551017160
Short name T397
Test name
Test status
Simulation time 28823347887 ps
CPU time 521.31 seconds
Started May 12 01:35:07 PM PDT 24
Finished May 12 01:43:49 PM PDT 24
Peak memory 200572 kb
Host smart-64bbbccf-d446-450f-8459-5e89aec862b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551017160 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2551017160
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1374810887
Short name T202
Test name
Test status
Simulation time 23919138 ps
CPU time 0.6 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 195908 kb
Host smart-8366c233-aa22-4f4f-9f00-98379948f07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374810887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1374810887
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3045996979
Short name T212
Test name
Test status
Simulation time 1138732106 ps
CPU time 15.61 seconds
Started May 12 01:35:08 PM PDT 24
Finished May 12 01:35:24 PM PDT 24
Peak memory 208788 kb
Host smart-1ed39a33-1218-4209-87a1-895ee12292b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045996979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3045996979
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2075549722
Short name T143
Test name
Test status
Simulation time 870920565 ps
CPU time 12.04 seconds
Started May 12 01:35:01 PM PDT 24
Finished May 12 01:35:14 PM PDT 24
Peak memory 200484 kb
Host smart-9caf3aeb-94f0-4eb5-876e-d8a9a08c95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075549722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2075549722
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.948444613
Short name T135
Test name
Test status
Simulation time 7787975061 ps
CPU time 395.61 seconds
Started May 12 01:35:10 PM PDT 24
Finished May 12 01:41:46 PM PDT 24
Peak memory 684124 kb
Host smart-a4a65606-ccfe-4547-9797-07fdc55414ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948444613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.948444613
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4288037676
Short name T414
Test name
Test status
Simulation time 7618642338 ps
CPU time 74.98 seconds
Started May 12 01:35:07 PM PDT 24
Finished May 12 01:36:22 PM PDT 24
Peak memory 200684 kb
Host smart-34ef3b60-1ab4-43d1-9453-95f05e03cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288037676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4288037676
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.408109064
Short name T18
Test name
Test status
Simulation time 381049414 ps
CPU time 3.4 seconds
Started May 12 01:35:09 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 200612 kb
Host smart-d57d2837-e383-4497-8696-eac45d86ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408109064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.408109064
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2649067526
Short name T223
Test name
Test status
Simulation time 136041840 ps
CPU time 1.37 seconds
Started May 12 01:35:09 PM PDT 24
Finished May 12 01:35:10 PM PDT 24
Peak memory 200576 kb
Host smart-3189bea3-66d8-4df8-b2e5-5d6caf596ae6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649067526 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2649067526
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.117579821
Short name T447
Test name
Test status
Simulation time 44537459540 ps
CPU time 467.03 seconds
Started May 12 01:35:01 PM PDT 24
Finished May 12 01:42:49 PM PDT 24
Peak memory 200612 kb
Host smart-ecae766b-e3ee-4747-9e05-9b86366bd27d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117579821 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.117579821
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.824753425
Short name T159
Test name
Test status
Simulation time 16055293 ps
CPU time 0.64 seconds
Started May 12 01:35:13 PM PDT 24
Finished May 12 01:35:14 PM PDT 24
Peak memory 196268 kb
Host smart-f43ee2ad-56b2-4433-aeb3-bc50c1aeb341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824753425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.824753425
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.40797255
Short name T456
Test name
Test status
Simulation time 1958388201 ps
CPU time 49.67 seconds
Started May 12 01:35:08 PM PDT 24
Finished May 12 01:35:58 PM PDT 24
Peak memory 224880 kb
Host smart-81d49fd8-dfaa-467a-aa7b-71c1549dd453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40797255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.40797255
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1944641938
Short name T116
Test name
Test status
Simulation time 228610736 ps
CPU time 5.37 seconds
Started May 12 01:35:10 PM PDT 24
Finished May 12 01:35:16 PM PDT 24
Peak memory 200624 kb
Host smart-e6a4b904-f256-4719-ba8e-3ca4494bbfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944641938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1944641938
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1543623383
Short name T156
Test name
Test status
Simulation time 1680024470 ps
CPU time 357.08 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:41:08 PM PDT 24
Peak memory 641860 kb
Host smart-1f8d03b9-26c1-4733-b8f2-7c65f38e085e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543623383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1543623383
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3901314307
Short name T216
Test name
Test status
Simulation time 1620432355 ps
CPU time 99.04 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:36:51 PM PDT 24
Peak memory 200320 kb
Host smart-c40703b6-9891-48db-8f8b-6ba81d8d3b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901314307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3901314307
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3702578201
Short name T395
Test name
Test status
Simulation time 226650196 ps
CPU time 1.35 seconds
Started May 12 01:35:07 PM PDT 24
Finished May 12 01:35:09 PM PDT 24
Peak memory 200564 kb
Host smart-508ca49b-521f-49d7-87ff-09c7756972b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702578201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3702578201
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3037498060
Short name T460
Test name
Test status
Simulation time 112286342 ps
CPU time 1.04 seconds
Started May 12 01:35:08 PM PDT 24
Finished May 12 01:35:09 PM PDT 24
Peak memory 200144 kb
Host smart-6b0f4eaf-356e-4de7-9e79-82da00283d8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037498060 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3037498060
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1419920019
Short name T357
Test name
Test status
Simulation time 172193965455 ps
CPU time 533.74 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:44:06 PM PDT 24
Peak memory 200616 kb
Host smart-9223455e-9936-460f-9b6c-816ad7b954a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419920019 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1419920019
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2988643106
Short name T469
Test name
Test status
Simulation time 13326407 ps
CPU time 0.57 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 195268 kb
Host smart-61e22006-86bb-4f02-b7f9-633742ef8c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988643106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2988643106
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1831299152
Short name T118
Test name
Test status
Simulation time 2411992607 ps
CPU time 35.68 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:48 PM PDT 24
Peak memory 229920 kb
Host smart-73a80ff7-f9ef-4fbb-87f7-9590dcba5e3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831299152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1831299152
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.994702948
Short name T468
Test name
Test status
Simulation time 715026194 ps
CPU time 9.38 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:21 PM PDT 24
Peak memory 200640 kb
Host smart-d84021d0-7c34-43e9-8488-8b887db86257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994702948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.994702948
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3417812536
Short name T420
Test name
Test status
Simulation time 1003696350 ps
CPU time 233.58 seconds
Started May 12 01:35:10 PM PDT 24
Finished May 12 01:39:04 PM PDT 24
Peak memory 442764 kb
Host smart-1b1548b0-face-49b8-a009-97a8eea5e7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417812536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3417812536
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.27427658
Short name T168
Test name
Test status
Simulation time 3173909878 ps
CPU time 45.1 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:57 PM PDT 24
Peak memory 200280 kb
Host smart-665ccba9-af28-449c-add7-276219835386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27427658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.27427658
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3234583506
Short name T312
Test name
Test status
Simulation time 195533932 ps
CPU time 1.93 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:35:15 PM PDT 24
Peak memory 200532 kb
Host smart-05428f91-ad5c-45c7-ac3d-e72c0e5634b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234583506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3234583506
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3678913751
Short name T140
Test name
Test status
Simulation time 30571399 ps
CPU time 1.24 seconds
Started May 12 01:35:10 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 200660 kb
Host smart-b2b48fb7-3a12-4612-beba-a5941a9c35bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678913751 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3678913751
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3694151470
Short name T478
Test name
Test status
Simulation time 105637305847 ps
CPU time 494.11 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:43:27 PM PDT 24
Peak memory 200596 kb
Host smart-03a44f5d-e39a-4f8c-8027-41ed3f57d716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694151470 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3694151470
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1547624159
Short name T444
Test name
Test status
Simulation time 13871855 ps
CPU time 0.57 seconds
Started May 12 01:35:16 PM PDT 24
Finished May 12 01:35:17 PM PDT 24
Peak memory 195316 kb
Host smart-beee7e76-ac68-460c-8e3e-d468684df2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547624159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1547624159
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.994647984
Short name T407
Test name
Test status
Simulation time 358771719 ps
CPU time 21.94 seconds
Started May 12 01:35:14 PM PDT 24
Finished May 12 01:35:36 PM PDT 24
Peak memory 220768 kb
Host smart-0fdaf31b-5340-43bf-81fe-294ba6bc6fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994647984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.994647984
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1021035101
Short name T347
Test name
Test status
Simulation time 416547971 ps
CPU time 21.92 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:35:35 PM PDT 24
Peak memory 200508 kb
Host smart-c02e029a-f0f5-4cca-abce-d2bfb4682570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021035101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1021035101
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.341505464
Short name T411
Test name
Test status
Simulation time 12020153207 ps
CPU time 855.33 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:49:28 PM PDT 24
Peak memory 719576 kb
Host smart-e619ed65-dc59-48df-b445-2ef9d7a85093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341505464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.341505464
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4195571463
Short name T199
Test name
Test status
Simulation time 1326845958 ps
CPU time 35.76 seconds
Started May 12 01:35:11 PM PDT 24
Finished May 12 01:35:48 PM PDT 24
Peak memory 200612 kb
Host smart-90486a15-1f9b-4f6f-964f-4120100be5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195571463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4195571463
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3066960235
Short name T171
Test name
Test status
Simulation time 44498420 ps
CPU time 0.96 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:35:14 PM PDT 24
Peak memory 200264 kb
Host smart-ae74e99d-fc3d-4573-9a0f-0a1a574b57d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066960235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3066960235
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.122896844
Short name T231
Test name
Test status
Simulation time 32980853620 ps
CPU time 432.99 seconds
Started May 12 01:35:12 PM PDT 24
Finished May 12 01:42:26 PM PDT 24
Peak memory 208824 kb
Host smart-364a0fd2-f7f3-419e-8507-204a2afe529b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122896844 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.122896844
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3463544085
Short name T161
Test name
Test status
Simulation time 50650234 ps
CPU time 1.12 seconds
Started May 12 01:35:13 PM PDT 24
Finished May 12 01:35:15 PM PDT 24
Peak memory 200232 kb
Host smart-681d4ef5-3deb-4b8c-ba1d-22e597d8649a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463544085 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3463544085
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.666754637
Short name T452
Test name
Test status
Simulation time 8001575610 ps
CPU time 441.57 seconds
Started May 12 01:35:13 PM PDT 24
Finished May 12 01:42:35 PM PDT 24
Peak memory 200660 kb
Host smart-b35befd9-5872-49b9-ab10-cf9e09ca90d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666754637 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.666754637
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2779408886
Short name T352
Test name
Test status
Simulation time 60824340 ps
CPU time 0.58 seconds
Started May 12 01:35:18 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 195232 kb
Host smart-5fe0b489-0c00-4783-86b3-59aa0457fce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779408886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2779408886
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3371564847
Short name T262
Test name
Test status
Simulation time 2501377340 ps
CPU time 43.05 seconds
Started May 12 01:35:19 PM PDT 24
Finished May 12 01:36:02 PM PDT 24
Peak memory 211952 kb
Host smart-c8c2eae0-2129-492e-9227-482801838c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371564847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3371564847
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1941098715
Short name T396
Test name
Test status
Simulation time 641256092 ps
CPU time 34.5 seconds
Started May 12 01:35:22 PM PDT 24
Finished May 12 01:35:57 PM PDT 24
Peak memory 200608 kb
Host smart-c34b843a-cc38-443b-ad82-a03ab5422e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941098715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1941098715
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1374477008
Short name T151
Test name
Test status
Simulation time 7849823608 ps
CPU time 1093.52 seconds
Started May 12 01:35:16 PM PDT 24
Finished May 12 01:53:30 PM PDT 24
Peak memory 756816 kb
Host smart-eb0c90c0-9c2d-434b-9305-f8a633315bb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374477008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1374477008
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1007857130
Short name T12
Test name
Test status
Simulation time 4538224160 ps
CPU time 19.69 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:35:41 PM PDT 24
Peak memory 200760 kb
Host smart-fdba0d3f-e7d2-4fc8-8766-ca0fb4462542
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007857130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1007857130
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3000661771
Short name T136
Test name
Test status
Simulation time 5786866802 ps
CPU time 46.64 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:36:07 PM PDT 24
Peak memory 200700 kb
Host smart-251db6f5-f1e1-4303-a2ab-2a4cbab3f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000661771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3000661771
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1778337380
Short name T166
Test name
Test status
Simulation time 142529440 ps
CPU time 4.55 seconds
Started May 12 01:35:15 PM PDT 24
Finished May 12 01:35:20 PM PDT 24
Peak memory 200552 kb
Host smart-b44236ce-fb50-47c9-9d96-76fe37525f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778337380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1778337380
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2038117281
Short name T26
Test name
Test status
Simulation time 507833234 ps
CPU time 1.31 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:35:22 PM PDT 24
Peak memory 200536 kb
Host smart-4d86c100-f449-4cad-b4ba-b3ae6c909437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038117281 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2038117281
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1760265057
Short name T303
Test name
Test status
Simulation time 7400692529 ps
CPU time 407.79 seconds
Started May 12 01:35:17 PM PDT 24
Finished May 12 01:42:05 PM PDT 24
Peak memory 200708 kb
Host smart-2f0ad3ab-3dcc-4fd4-97c4-9cfd2b31fb2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760265057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1760265057
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3262982458
Short name T448
Test name
Test status
Simulation time 121517331 ps
CPU time 0.6 seconds
Started May 12 01:35:18 PM PDT 24
Finished May 12 01:35:19 PM PDT 24
Peak memory 197040 kb
Host smart-208499b7-bfd0-4f0f-bc17-ab9c09e3c92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262982458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3262982458
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4226691229
Short name T14
Test name
Test status
Simulation time 1892974281 ps
CPU time 54.91 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:36:15 PM PDT 24
Peak memory 233512 kb
Host smart-3d4df8c0-6cc7-4d6e-88ef-a7ffb29eb292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226691229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4226691229
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2354585171
Short name T221
Test name
Test status
Simulation time 5496494849 ps
CPU time 47.96 seconds
Started May 12 01:35:17 PM PDT 24
Finished May 12 01:36:06 PM PDT 24
Peak memory 200724 kb
Host smart-1cc80f40-0825-4dc9-a890-1fad2b20beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354585171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2354585171
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2534460385
Short name T424
Test name
Test status
Simulation time 956445543 ps
CPU time 60.21 seconds
Started May 12 01:35:16 PM PDT 24
Finished May 12 01:36:17 PM PDT 24
Peak memory 401752 kb
Host smart-2e117ccd-1846-4850-95d3-ecf0c318c04b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534460385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2534460385
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1425427336
Short name T184
Test name
Test status
Simulation time 31659143248 ps
CPU time 108.7 seconds
Started May 12 01:35:19 PM PDT 24
Finished May 12 01:37:08 PM PDT 24
Peak memory 200680 kb
Host smart-7193c898-2962-46ce-82ba-edd43feca75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425427336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1425427336
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3819742251
Short name T389
Test name
Test status
Simulation time 172201727 ps
CPU time 6 seconds
Started May 12 01:35:18 PM PDT 24
Finished May 12 01:35:25 PM PDT 24
Peak memory 200560 kb
Host smart-438374c0-61f0-4459-a1cb-b5794b419d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819742251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3819742251
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2119188103
Short name T229
Test name
Test status
Simulation time 10446370723 ps
CPU time 559.9 seconds
Started May 12 01:35:17 PM PDT 24
Finished May 12 01:44:38 PM PDT 24
Peak memory 223304 kb
Host smart-d45b724a-8c23-4b28-84a7-eec2d040552b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119188103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2119188103
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1974595682
Short name T132
Test name
Test status
Simulation time 57827704 ps
CPU time 1.1 seconds
Started May 12 01:35:17 PM PDT 24
Finished May 12 01:35:18 PM PDT 24
Peak memory 200208 kb
Host smart-1a8e6810-02b9-4f17-890e-c2fbb0337794
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974595682 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1974595682
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1166142554
Short name T180
Test name
Test status
Simulation time 7718317417 ps
CPU time 451.23 seconds
Started May 12 01:35:16 PM PDT 24
Finished May 12 01:42:47 PM PDT 24
Peak memory 200648 kb
Host smart-79719546-3481-4927-a570-d8844748551b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166142554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1166142554
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1520834123
Short name T25
Test name
Test status
Simulation time 371532436 ps
CPU time 7.98 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:35:29 PM PDT 24
Peak memory 200556 kb
Host smart-66ad2cbb-a808-445f-a857-2197ec525309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520834123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1520834123
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4062525116
Short name T163
Test name
Test status
Simulation time 22838185 ps
CPU time 0.58 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:35:21 PM PDT 24
Peak memory 195232 kb
Host smart-3aa376b9-b0c8-4364-ac10-886d9655d4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062525116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4062525116
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2207409555
Short name T394
Test name
Test status
Simulation time 220294301 ps
CPU time 16.55 seconds
Started May 12 01:35:23 PM PDT 24
Finished May 12 01:35:40 PM PDT 24
Peak memory 229616 kb
Host smart-94f1711f-4ddc-4c0d-98c0-e151a35a1d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2207409555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2207409555
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3439187465
Short name T36
Test name
Test status
Simulation time 3351092316 ps
CPU time 30.65 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:35:51 PM PDT 24
Peak memory 200712 kb
Host smart-562d9bff-310b-4273-b460-dfd7b0d2a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439187465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3439187465
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2594159970
Short name T130
Test name
Test status
Simulation time 11752329671 ps
CPU time 637.4 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:45:58 PM PDT 24
Peak memory 698344 kb
Host smart-9668f90c-a4da-4069-8f43-7026dfd4342d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594159970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2594159970
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3190908995
Short name T470
Test name
Test status
Simulation time 4836548181 ps
CPU time 85.18 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 01:36:45 PM PDT 24
Peak memory 200668 kb
Host smart-5f5b201b-dc86-4306-a00c-335613583332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190908995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3190908995
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.344250884
Short name T413
Test name
Test status
Simulation time 546827561 ps
CPU time 6.29 seconds
Started May 12 01:35:19 PM PDT 24
Finished May 12 01:35:25 PM PDT 24
Peak memory 200556 kb
Host smart-cdcfb4cb-9f96-42ec-866e-3bdfe218e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344250884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.344250884
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3707405517
Short name T363
Test name
Test status
Simulation time 13713546278 ps
CPU time 1704.43 seconds
Started May 12 01:35:20 PM PDT 24
Finished May 12 02:03:45 PM PDT 24
Peak memory 795872 kb
Host smart-c72f4364-ce0d-43d2-85ef-453de02d00e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707405517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3707405517
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1434929328
Short name T318
Test name
Test status
Simulation time 846480886 ps
CPU time 1.34 seconds
Started May 12 01:35:21 PM PDT 24
Finished May 12 01:35:22 PM PDT 24
Peak memory 200516 kb
Host smart-84d0f2e0-87d3-4079-b927-b6099b20ba2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434929328 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1434929328
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.4124320086
Short name T337
Test name
Test status
Simulation time 59051662912 ps
CPU time 543.6 seconds
Started May 12 01:35:18 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 200592 kb
Host smart-98a5b71b-977c-47b7-978a-80881235158f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124320086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.4124320086
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1618833173
Short name T316
Test name
Test status
Simulation time 17226996 ps
CPU time 0.58 seconds
Started May 12 01:33:38 PM PDT 24
Finished May 12 01:33:39 PM PDT 24
Peak memory 195160 kb
Host smart-7ca9418b-23dc-4ba4-a751-8535ee4be4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618833173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1618833173
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2967642332
Short name T115
Test name
Test status
Simulation time 1042485187 ps
CPU time 51.7 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:34:28 PM PDT 24
Peak memory 222412 kb
Host smart-56503c42-b4af-4dda-9f9c-3b7b8102c00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967642332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2967642332
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1006432630
Short name T219
Test name
Test status
Simulation time 14791287747 ps
CPU time 32.78 seconds
Started May 12 01:33:35 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 200860 kb
Host smart-5606b675-4b8f-4de8-952a-b23131efec06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006432630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1006432630
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1624164135
Short name T459
Test name
Test status
Simulation time 5068675452 ps
CPU time 705.57 seconds
Started May 12 01:33:36 PM PDT 24
Finished May 12 01:45:23 PM PDT 24
Peak memory 694424 kb
Host smart-8e30d9b4-fa74-466a-9b4b-18bbba7a41c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624164135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1624164135
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.330456553
Short name T361
Test name
Test status
Simulation time 4609114673 ps
CPU time 28.85 seconds
Started May 12 01:33:34 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200652 kb
Host smart-c038bfba-7a08-4eb4-a5ed-595e907ce4c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330456553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.330456553
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3333410302
Short name T224
Test name
Test status
Simulation time 9891580079 ps
CPU time 48.23 seconds
Started May 12 01:33:38 PM PDT 24
Finished May 12 01:34:27 PM PDT 24
Peak memory 200744 kb
Host smart-5260b531-491d-47e1-8908-7aef733b3e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333410302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3333410302
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2237647582
Short name T406
Test name
Test status
Simulation time 110207675 ps
CPU time 3.72 seconds
Started May 12 01:33:37 PM PDT 24
Finished May 12 01:33:42 PM PDT 24
Peak memory 200536 kb
Host smart-b1b3ed6b-ca1b-4da9-858a-e73119261131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237647582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2237647582
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2733387769
Short name T443
Test name
Test status
Simulation time 32351361 ps
CPU time 1.2 seconds
Started May 12 01:33:39 PM PDT 24
Finished May 12 01:33:41 PM PDT 24
Peak memory 200616 kb
Host smart-37e72574-30f6-47f6-ab44-4acce7607d15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733387769 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2733387769
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2697976426
Short name T402
Test name
Test status
Simulation time 498703099157 ps
CPU time 467.73 seconds
Started May 12 01:33:37 PM PDT 24
Finished May 12 01:41:26 PM PDT 24
Peak memory 200576 kb
Host smart-45f12943-92de-479f-ae49-2a51bb043917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697976426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2697976426
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3182684391
Short name T220
Test name
Test status
Simulation time 49197420 ps
CPU time 0.59 seconds
Started May 12 01:33:43 PM PDT 24
Finished May 12 01:33:44 PM PDT 24
Peak memory 195268 kb
Host smart-905c4a2f-b5eb-4c6a-b550-3aaa7ae09637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182684391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3182684391
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3346353148
Short name T300
Test name
Test status
Simulation time 1690561323 ps
CPU time 43.98 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 232412 kb
Host smart-e9bc37b7-83d2-432a-a6a5-f24bb29d8210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346353148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3346353148
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2977278855
Short name T422
Test name
Test status
Simulation time 21803763904 ps
CPU time 14.39 seconds
Started May 12 01:33:38 PM PDT 24
Finished May 12 01:33:53 PM PDT 24
Peak memory 200928 kb
Host smart-89f4b3c8-6f38-4f1b-a117-cd1db9a393f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977278855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2977278855
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1954392492
Short name T155
Test name
Test status
Simulation time 4616988511 ps
CPU time 1106.43 seconds
Started May 12 01:33:39 PM PDT 24
Finished May 12 01:52:06 PM PDT 24
Peak memory 771136 kb
Host smart-be43bff0-be2e-4d1d-9a40-6398076115d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954392492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1954392492
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.416611931
Short name T385
Test name
Test status
Simulation time 190580054 ps
CPU time 10.25 seconds
Started May 12 01:33:39 PM PDT 24
Finished May 12 01:33:50 PM PDT 24
Peak memory 200344 kb
Host smart-186d0046-1ee4-46a0-b681-83da63c559ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416611931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.416611931
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.925521867
Short name T260
Test name
Test status
Simulation time 4913760533 ps
CPU time 92.9 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:35:13 PM PDT 24
Peak memory 200664 kb
Host smart-d439985e-ec8c-4e67-960c-1e21eaf870de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925521867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.925521867
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.999010865
Short name T209
Test name
Test status
Simulation time 91514877 ps
CPU time 3.32 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:33:44 PM PDT 24
Peak memory 200556 kb
Host smart-ee706a45-433a-4fd9-82a8-fd54af77e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999010865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.999010865
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1372412023
Short name T11
Test name
Test status
Simulation time 13868087322 ps
CPU time 89.38 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:35:12 PM PDT 24
Peak memory 200764 kb
Host smart-82994789-c680-4160-b868-1344b6862026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372412023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1372412023
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.651214634
Short name T134
Test name
Test status
Simulation time 32504069 ps
CPU time 1.31 seconds
Started May 12 01:33:42 PM PDT 24
Finished May 12 01:33:44 PM PDT 24
Peak memory 200492 kb
Host smart-04335411-3ebc-4dc1-8d47-5855445ed934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651214634 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.651214634
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1640065156
Short name T3
Test name
Test status
Simulation time 31938854848 ps
CPU time 456.16 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:41:18 PM PDT 24
Peak memory 200544 kb
Host smart-049447f1-63e5-4df3-8af0-3311bbae163f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640065156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1640065156
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4081547457
Short name T283
Test name
Test status
Simulation time 11718955 ps
CPU time 0.59 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:33:41 PM PDT 24
Peak memory 195316 kb
Host smart-9a128a06-4e48-464f-8922-07c99a3f2477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081547457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4081547457
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3104520671
Short name T446
Test name
Test status
Simulation time 564038844 ps
CPU time 26.96 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:34:07 PM PDT 24
Peak memory 208816 kb
Host smart-d98885ae-7ea2-46b2-92e1-530cd868a9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104520671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3104520671
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2989417572
Short name T237
Test name
Test status
Simulation time 4386744954 ps
CPU time 33.06 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:34:15 PM PDT 24
Peak memory 200612 kb
Host smart-cf551f08-d4c5-4224-b79d-2af07540854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989417572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2989417572
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1483512822
Short name T279
Test name
Test status
Simulation time 515597486 ps
CPU time 125.28 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:35:46 PM PDT 24
Peak memory 602776 kb
Host smart-d0e4acc4-3387-4e65-a59b-f760cf7f0249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483512822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1483512822
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3779550905
Short name T346
Test name
Test status
Simulation time 9982631634 ps
CPU time 33.78 seconds
Started May 12 01:33:39 PM PDT 24
Finished May 12 01:34:13 PM PDT 24
Peak memory 200720 kb
Host smart-4fc72e3a-f821-4120-bea4-4d4bde1c9732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779550905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3779550905
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2173971144
Short name T9
Test name
Test status
Simulation time 231319055 ps
CPU time 3.87 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:33:45 PM PDT 24
Peak memory 200532 kb
Host smart-2cc857ad-ca70-4c71-b784-edc993640fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173971144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2173971144
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1946946666
Short name T19
Test name
Test status
Simulation time 7203250009 ps
CPU time 46.33 seconds
Started May 12 01:33:42 PM PDT 24
Finished May 12 01:34:29 PM PDT 24
Peak memory 200696 kb
Host smart-c191927e-287e-41be-a6b4-2614e3197ac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946946666 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1946946666
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1511277318
Short name T364
Test name
Test status
Simulation time 471314549 ps
CPU time 1.24 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:33:43 PM PDT 24
Peak memory 200464 kb
Host smart-7f1dcf4e-1256-4917-a1ca-cc27b8059b6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511277318 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1511277318
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.142349792
Short name T415
Test name
Test status
Simulation time 42157342230 ps
CPU time 520.4 seconds
Started May 12 01:33:41 PM PDT 24
Finished May 12 01:42:22 PM PDT 24
Peak memory 200544 kb
Host smart-021c0da4-eba8-4cdf-8c19-f7bfed601c25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142349792 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.142349792
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1855473974
Short name T208
Test name
Test status
Simulation time 74164633 ps
CPU time 0.58 seconds
Started May 12 01:33:42 PM PDT 24
Finished May 12 01:33:43 PM PDT 24
Peak memory 195304 kb
Host smart-765512d3-87ce-4785-a78d-ada12531cdc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855473974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1855473974
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3189246229
Short name T287
Test name
Test status
Simulation time 5678820179 ps
CPU time 64.65 seconds
Started May 12 01:33:45 PM PDT 24
Finished May 12 01:34:50 PM PDT 24
Peak memory 233432 kb
Host smart-f77d3acf-e096-4660-9d99-f218687ac5be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189246229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3189246229
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3073043932
Short name T100
Test name
Test status
Simulation time 6150893761 ps
CPU time 59.84 seconds
Started May 12 01:33:44 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200664 kb
Host smart-08d1067e-416e-4c98-a4f6-ac119b080737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073043932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3073043932
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1588986279
Short name T95
Test name
Test status
Simulation time 3352397127 ps
CPU time 111.59 seconds
Started May 12 01:33:43 PM PDT 24
Finished May 12 01:35:35 PM PDT 24
Peak memory 573636 kb
Host smart-a1fa10ca-c4bf-4c49-9329-42805f980a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588986279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1588986279
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2154023417
Short name T383
Test name
Test status
Simulation time 1795572225 ps
CPU time 17.83 seconds
Started May 12 01:33:44 PM PDT 24
Finished May 12 01:34:03 PM PDT 24
Peak memory 200440 kb
Host smart-eeb260a2-7ec4-4de5-96f3-f53c84fa4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154023417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2154023417
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2051073262
Short name T294
Test name
Test status
Simulation time 349420725 ps
CPU time 2.71 seconds
Started May 12 01:33:40 PM PDT 24
Finished May 12 01:33:44 PM PDT 24
Peak memory 200640 kb
Host smart-886c73ac-f1aa-4e06-b7f7-008d75d1dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051073262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2051073262
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3785424627
Short name T462
Test name
Test status
Simulation time 99605188 ps
CPU time 1.02 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:33:48 PM PDT 24
Peak memory 200076 kb
Host smart-fe6c9843-b4d3-4147-9f48-040f3b0af9e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785424627 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3785424627
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1583098938
Short name T313
Test name
Test status
Simulation time 31051947855 ps
CPU time 551.37 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:42:59 PM PDT 24
Peak memory 200604 kb
Host smart-43fada8b-d5af-4b5c-bb65-ef787507fe98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583098938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1583098938
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3080457058
Short name T403
Test name
Test status
Simulation time 21800629 ps
CPU time 0.6 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:33:48 PM PDT 24
Peak memory 196276 kb
Host smart-603b07ba-e487-4489-ab7d-7e04163881b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080457058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3080457058
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2266874480
Short name T457
Test name
Test status
Simulation time 621897333 ps
CPU time 37.83 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:34:25 PM PDT 24
Peak memory 229644 kb
Host smart-9bb1b252-4fb6-469b-ba3f-cf8c11b79d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266874480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2266874480
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1829686066
Short name T64
Test name
Test status
Simulation time 1968332382 ps
CPU time 30.26 seconds
Started May 12 01:33:44 PM PDT 24
Finished May 12 01:34:14 PM PDT 24
Peak memory 200720 kb
Host smart-113c0d88-5f15-42a3-bb93-4a9f1ba56fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829686066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1829686066
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.883409625
Short name T360
Test name
Test status
Simulation time 2946968452 ps
CPU time 737.84 seconds
Started May 12 01:33:45 PM PDT 24
Finished May 12 01:46:04 PM PDT 24
Peak memory 718612 kb
Host smart-b6367e4f-e6d7-4acf-be41-e064c51fac79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883409625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.883409625
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.873136653
Short name T345
Test name
Test status
Simulation time 150616243 ps
CPU time 0.66 seconds
Started May 12 01:33:46 PM PDT 24
Finished May 12 01:33:47 PM PDT 24
Peak memory 197952 kb
Host smart-d8c49060-d84f-4a34-bc97-bfa4996c434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873136653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.873136653
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2234957562
Short name T270
Test name
Test status
Simulation time 115711029 ps
CPU time 2.1 seconds
Started May 12 01:33:43 PM PDT 24
Finished May 12 01:33:46 PM PDT 24
Peak memory 200608 kb
Host smart-73a95624-7e8e-4388-94b2-84b260888cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234957562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2234957562
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.732008837
Short name T234
Test name
Test status
Simulation time 640381404 ps
CPU time 1.25 seconds
Started May 12 01:33:43 PM PDT 24
Finished May 12 01:33:45 PM PDT 24
Peak memory 200456 kb
Host smart-ca2e0cbc-247a-435f-941c-87387a9cbb69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732008837 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.732008837
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1382645572
Short name T78
Test name
Test status
Simulation time 7398878356 ps
CPU time 420.3 seconds
Started May 12 01:33:44 PM PDT 24
Finished May 12 01:40:45 PM PDT 24
Peak memory 200732 kb
Host smart-b217f90e-fcde-4e76-b58c-9489aee664d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382645572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1382645572
Directory /workspace/9.hmac_test_sha_vectors/latest
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