Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5746562	1			T1	22541		T2	8899		T3	28
all_values[1]	5746562	1			T1	22541		T2	8899		T3	28
all_values[2]	5746562	1			T1	22541		T2	8899		T3	28

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71377

1

T1

242

T4

3

T5

1896

auto[1]

17168309

1

T1

67381

T2

26697

T3

84

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15776278

1

T1

52334

T2

20719

T3

80

auto[1]

1463408

1

T1

15289

T2

5978

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24469	1			T1	240		T5	1894		T12	11
all_values[0]	auto[0]	auto[1]	193	1			T1	2		T5	2		T12	2
all_values[0]	auto[1]	auto[0]	5706986	1			T1	22290		T2	8898		T3	24
all_values[0]	auto[1]	auto[1]	14914	1			T1	9		T2	1		T3	4
all_values[1]	auto[0]	auto[0]	21631	1			T12	13		T111	514		T18	4
all_values[1]	auto[0]	auto[1]	100	1			T33	8		T29	3		T112	3
all_values[1]	auto[1]	auto[0]	5724717	1			T1	22541		T2	8899		T3	28
all_values[1]	auto[1]	auto[1]	114	1			T27	2		T33	7		T84	1
all_values[2]	auto[0]	auto[0]	15758	1			T4	1		T22	2		T113	2
all_values[2]	auto[0]	auto[1]	9226	1			T4	2		T22	2		T114	9
all_values[2]	auto[1]	auto[0]	4282717	1			T1	7263		T2	2922		T3	28
all_values[2]	auto[1]	auto[1]	1438861	1			T1	15278		T2	5977		T4	155