Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911464

1

T1

12752

T2

328

T3

23

auto[1]

834697

1

T1

9678

T2

2167

T4

95

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

816346

1

T1

13550

T2

1972

T4

163

auto[1]

2929815

1

T1

8880

T2

523

T3

23

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445303

1

T2

330

T4

158

T6

37176

auto[1]

1300858

1

T1

22430

T2

2165

T3

23

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3118410	1			T1	19903		T2	2462		T3	17
fifo_depth[1]	119016	1			T1	255		T2	21		T3	2
fifo_depth[2]	92308	1			T1	249		T2	9		T3	3
fifo_depth[3]	70470	1			T1	294		T2	2		T3	1
fifo_depth[4]	56438	1			T1	266		T2	1		T4	2
fifo_depth[5]	46917	1			T1	274		T4	1		T5	57
fifo_depth[6]	43717	1			T1	255		T5	55		T9	91
fifo_depth[7]	35650	1			T1	244		T5	43		T9	98

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627751

1

T1

2527

T2

33

T3

6

auto[1]

3118410

1

T1

19903

T2

2462

T3

17

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3742426

1

T1

22430

T2

2495

T3

23

auto[1]

3735

1

T7

1

T11

1

T18

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

22301

1

T11

1

T23

43

T24

3

auto[0]

auto[0]

auto[0]

auto[1]

18654

1

T7

2

T10

392

T11

3

auto[0]

auto[0]

auto[1]

auto[0]

389800

1

T6

15735

T7

4

T10

309

auto[0]

auto[0]

auto[1]

auto[1]

18504

1

T7

5

T11

1

T23

53

auto[0]

auto[1]

auto[0]

auto[0]

50335

1

T1

951

T4

6

T8

1226

auto[0]

auto[1]

auto[0]

auto[1]

39160

1

T1

1576

T4

2

T8

269

auto[0]

auto[1]

auto[1]

auto[0]

46446

1

T3

6

T4

2

T9

333

auto[0]

auto[1]

auto[1]

auto[1]

42551

1

T2

33

T5

590

T9

635

auto[1]

auto[0]

auto[0]

auto[0]

67409

1

T2

328

T4

60

T7

4

auto[1]

auto[0]

auto[0]

auto[1]

64033

1

T4

24

T7

1

T10

802

auto[1]

auto[0]

auto[1]

auto[0]

1786279

1

T4

43

T6

21441

T7

2

auto[1]

auto[0]

auto[1]

auto[1]

78323

1

T2

2

T4

31

T7

5

auto[1]

auto[1]

auto[0]

auto[0]

269963

1

T1

3576

T4

39

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

284491

1

T1

7447

T2

1644

T4

32

auto[1]

auto[1]

auto[1]

auto[0]

278931

1

T1

8225

T3

17

T4

65

auto[1]

auto[1]

auto[1]

auto[1]

288981

1

T1

655

T2

488

T4

6

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

87836

1

T2

328

T4

60

T7

4

auto[0]

auto[0]

auto[0]

auto[1]

82505

1

T4

24

T7

3

T10

1194

auto[0]

auto[0]

auto[1]

auto[0]

2175551

1

T4

43

T6

37176

T7

6

auto[0]

auto[0]

auto[1]

auto[1]

96624

1

T2

2

T4

31

T7

10

auto[0]

auto[1]

auto[0]

auto[0]

319959

1

T1

4527

T4

45

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

323619

1

T1

9023

T2

1644

T4

34

auto[0]

auto[1]

auto[1]

auto[0]

325254

1

T1

8225

T3

23

T4

67

auto[0]

auto[1]

auto[1]

auto[1]

331078

1

T1

655

T2

521

T4

6

auto[1]

auto[0]

auto[0]

auto[0]

1874

1

T45

1

T32

1569

T49

1

auto[1]

auto[0]

auto[0]

auto[1]

182

1

T18

1

T47

1

T32

1

auto[1]

auto[0]

auto[1]

auto[0]

528

1

T32

270

T84

60

T63

31

auto[1]

auto[0]

auto[1]

auto[1]

203

1

T47

1

T125

1

T103

7

auto[1]

auto[1]

auto[0]

auto[0]

339

1

T46

1

T32

14

T126

1

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T7

1

T11

1

T45

1

auto[1]

auto[1]

auto[1]

auto[0]

123

1

T84

2

T103

25

T127

1

auto[1]

auto[1]

auto[1]

auto[1]

454

1

T50

2

T103

11

T63

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	67409	1			T2	328		T4	60		T7	4
fifo_depth[0]	auto[0]	auto[0]	auto[1]	64033	1			T4	24		T7	1		T10	802
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1786279	1			T4	43		T6	21441		T7	2
fifo_depth[0]	auto[0]	auto[1]	auto[1]	78323	1			T2	2		T4	31		T7	5
fifo_depth[0]	auto[1]	auto[0]	auto[0]	269963	1			T1	3576		T4	39		T5	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	284491	1			T1	7447		T2	1644		T4	32
fifo_depth[0]	auto[1]	auto[1]	auto[0]	278931	1			T1	8225		T3	17		T4	65
fifo_depth[0]	auto[1]	auto[1]	auto[1]	288981	1			T1	655		T2	488		T4	6
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1357	1			T23	30		T24	3		T111	1
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1069	1			T10	34		T34	4		T24	77
fifo_depth[1]	auto[0]	auto[1]	auto[0]	97919	1			T6	2464		T10	36		T17	2469
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1623	1			T23	34		T24	19		T111	25
fifo_depth[1]	auto[1]	auto[0]	auto[0]	4431	1			T1	96		T4	3		T8	116
fifo_depth[1]	auto[1]	auto[0]	auto[1]	3971	1			T1	159		T4	1		T8	27
fifo_depth[1]	auto[1]	auto[1]	auto[0]	4578	1			T3	2		T9	37		T8	80
fifo_depth[1]	auto[1]	auto[1]	auto[1]	4068	1			T2	21		T5	60		T9	66
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1518	1			T23	6		T111	1		T128	1
fifo_depth[2]	auto[0]	auto[0]	auto[1]	922	1			T10	48		T24	24		T111	1
fifo_depth[2]	auto[0]	auto[1]	auto[0]	71617	1			T6	2438		T10	39		T17	2310
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1400	1			T23	14		T24	7		T111	3
fifo_depth[2]	auto[1]	auto[0]	auto[0]	4254	1			T1	93		T4	2		T8	141
fifo_depth[2]	auto[1]	auto[0]	auto[1]	3972	1			T1	156		T4	1		T8	31
fifo_depth[2]	auto[1]	auto[1]	auto[0]	4594	1			T3	3		T9	40		T8	86
fifo_depth[2]	auto[1]	auto[1]	auto[1]	4031	1			T2	9		T5	66		T9	60
fifo_depth[3]	auto[0]	auto[0]	auto[0]	916	1			T23	7		T111	1		T129	74
fifo_depth[3]	auto[0]	auto[0]	auto[1]	628	1			T10	43		T24	7		T129	50
fifo_depth[3]	auto[0]	auto[1]	auto[0]	52535	1			T6	2191		T10	31		T17	1936
fifo_depth[3]	auto[0]	auto[1]	auto[1]	993	1			T23	5		T111	3		T27	11
fifo_depth[3]	auto[1]	auto[0]	auto[0]	3990	1			T1	112		T8	136		T111	5
fifo_depth[3]	auto[1]	auto[0]	auto[1]	3524	1			T1	182		T8	36		T10	5
fifo_depth[3]	auto[1]	auto[1]	auto[0]	4200	1			T3	1		T9	34		T8	93
fifo_depth[3]	auto[1]	auto[1]	auto[1]	3684	1			T2	2		T5	75		T9	73
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1270	1			T129	71		T27	3		T32	48
fifo_depth[4]	auto[0]	auto[0]	auto[1]	836	1			T10	52		T24	1		T129	53
fifo_depth[4]	auto[0]	auto[1]	auto[0]	37480	1			T6	1917		T10	39		T17	1421
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1053	1			T24	2		T111	1		T27	3
fifo_depth[4]	auto[1]	auto[0]	auto[0]	3938	1			T1	101		T4	1		T8	129
fifo_depth[4]	auto[1]	auto[0]	auto[1]	3776	1			T1	165		T8	28		T10	7
fifo_depth[4]	auto[1]	auto[1]	auto[0]	4313	1			T4	1		T9	31		T8	77
fifo_depth[4]	auto[1]	auto[1]	auto[1]	3772	1			T2	1		T5	62		T9	70
fifo_depth[5]	auto[0]	auto[0]	auto[0]	855	1			T129	67		T27	1		T32	52
fifo_depth[5]	auto[0]	auto[0]	auto[1]	551	1			T10	41		T129	58		T32	27
fifo_depth[5]	auto[0]	auto[1]	auto[0]	30106	1			T6	1682		T10	24		T17	1146
fifo_depth[5]	auto[0]	auto[1]	auto[1]	827	1			T130	3		T106	1		T131	23
fifo_depth[5]	auto[1]	auto[0]	auto[0]	3737	1			T1	106		T8	145		T113	94
fifo_depth[5]	auto[1]	auto[0]	auto[1]	3560	1			T1	168		T8	35		T10	7
fifo_depth[5]	auto[1]	auto[1]	auto[0]	3886	1			T4	1		T9	39		T8	74
fifo_depth[5]	auto[1]	auto[1]	auto[1]	3395	1			T5	57		T9	83		T8	174
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1370	1			T129	64		T32	56		T132	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	961	1			T10	32		T129	53		T32	156
fifo_depth[6]	auto[0]	auto[1]	auto[0]	25432	1			T6	1472		T10	31		T17	915
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1002	1			T32	14		T130	2		T108	2
fifo_depth[6]	auto[1]	auto[0]	auto[0]	3821	1			T1	85		T8	123		T113	96
fifo_depth[6]	auto[1]	auto[0]	auto[1]	3723	1			T1	170		T8	27		T10	4
fifo_depth[6]	auto[1]	auto[1]	auto[0]	4081	1			T9	27		T8	74		T37	89
fifo_depth[6]	auto[1]	auto[1]	auto[1]	3327	1			T5	55		T9	64		T8	163
fifo_depth[7]	auto[0]	auto[0]	auto[0]	767	1			T129	68		T32	50		T108	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	542	1			T10	35		T129	45		T32	23
fifo_depth[7]	auto[0]	auto[1]	auto[0]	20313	1			T6	1184		T10	30		T17	759
fifo_depth[7]	auto[0]	auto[1]	auto[1]	869	1			T32	1		T131	24		T78	68
fifo_depth[7]	auto[1]	auto[0]	auto[0]	3486	1			T1	90		T8	119		T113	97
fifo_depth[7]	auto[1]	auto[0]	auto[1]	3131	1			T1	154		T8	28		T10	4
fifo_depth[7]	auto[1]	auto[1]	auto[0]	3497	1			T9	24		T8	77		T37	76
fifo_depth[7]	auto[1]	auto[1]	auto[1]	3045	1			T5	43		T9	74		T8	147