Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5746562	1			T1	22541		T2	8899		T3	28
all_pins[1]	5746562	1			T1	22541		T2	8899		T3	28
all_pins[2]	5746562	1			T1	22541		T2	8899		T3	28

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	15785603	1			T1	52336		T2	20719		T3	80
values[0x1]	1454083	1			T1	15287		T2	5978		T3	4
transitions[0x0=>0x1]	1453996	1			T1	15287		T2	5978		T3	4
transitions[0x1=>0x0]	1454004	1			T1	15287		T2	5978		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5731458	1			T1	22532		T2	8898		T3	24
all_pins[0]	values[0x1]	15104	1			T1	9		T2	1		T3	4
all_pins[0]	transitions[0x0=>0x1]	15076	1			T1	9		T2	1		T3	4
all_pins[0]	transitions[0x1=>0x0]	1438841	1			T1	15278		T2	5977		T4	155
all_pins[1]	values[0x0]	5746444	1			T1	22541		T2	8899		T3	28
all_pins[1]	values[0x1]	118	1			T27	2		T33	7		T84	1
all_pins[1]	transitions[0x0=>0x1]	89	1			T27	1		T33	5		T84	1
all_pins[1]	transitions[0x1=>0x0]	15075	1			T1	9		T2	1		T3	4
all_pins[2]	values[0x0]	4307701	1			T1	7263		T2	2922		T3	28
all_pins[2]	values[0x1]	1438861	1			T1	15278		T2	5977		T4	155
all_pins[2]	transitions[0x0=>0x1]	1438831	1			T1	15278		T2	5977		T4	155
all_pins[2]	transitions[0x1=>0x0]	88	1			T27	1		T33	2		T84	1