Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 461 1 T27 7 T33 27 T29 11
all_values[1] 461 1 T27 7 T33 27 T29 11
all_values[2] 461 1 T27 7 T33 27 T29 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 760 1 T27 10 T33 46 T29 16
auto[1] 623 1 T27 11 T33 35 T29 17


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 467 1 T27 8 T33 15 T29 9
auto[1] 916 1 T27 13 T33 66 T29 24


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 774 1 T27 11 T33 31 T29 18
auto[1] 609 1 T27 10 T33 50 T29 15


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 104 1 T27 1 T33 4 T29 2
all_values[0] auto[0] auto[0] auto[1] 53 1 T27 1 T33 3 T29 3
all_values[0] auto[0] auto[1] auto[0] 57 1 T33 1 T29 2 T112 2
all_values[0] auto[0] auto[1] auto[1] 52 1 T33 2 T112 1 T71 2
all_values[0] auto[1] auto[0] auto[1] 111 1 T27 3 T33 11 T29 2
all_values[0] auto[1] auto[1] auto[1] 84 1 T27 2 T33 6 T29 2
all_values[1] auto[0] auto[0] auto[0] 70 1 T27 2 T33 3 T29 3
all_values[1] auto[0] auto[0] auto[1] 53 1 T33 3 T29 3 T71 2
all_values[1] auto[0] auto[1] auto[0] 71 1 T27 2 T33 3 T112 1
all_values[1] auto[0] auto[1] auto[1] 63 1 T27 1 T33 3 T29 1
all_values[1] auto[1] auto[0] auto[1] 102 1 T27 1 T33 8 T29 2
all_values[1] auto[1] auto[1] auto[1] 102 1 T27 1 T33 7 T29 2
all_values[2] auto[0] auto[0] auto[0] 95 1 T27 1 T33 3 T71 7
all_values[2] auto[0] auto[0] auto[1] 48 1 T33 3 T29 1 T112 1
all_values[2] auto[0] auto[1] auto[0] 70 1 T27 2 T33 1 T29 2
all_values[2] auto[0] auto[1] auto[1] 38 1 T27 1 T33 2 T29 1
all_values[2] auto[1] auto[0] auto[1] 124 1 T27 1 T33 8 T112 1
all_values[2] auto[1] auto[1] auto[1] 86 1 T27 2 T33 10 T29 7


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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