Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	1113	1			T1	6		T4	3		T5	1
sha2_384	1106	1			T2	1		T4	12		T5	1
sha2_256	12058	1			T1	4		T3	4		T4	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12689

1

T1

3

T3

4

T4

11

auto[1]

1588

1

T1

7

T2

1

T4

11

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T1

8

T4

12

T9

1

auto[1]

12674

1

T1

2

T2

1

T3

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

1706

1

T1

10

T2

1

T3

4

disabled

12571

1

T4

15

T6

194

T7

11

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	522	1			T4	8		T7	1		T11	1
key_1024	441	1			T2	1		T4	2		T8	1
key_512	541	1			T1	1		T4	3		T8	6
key_384	542	1			T1	1		T5	2		T9	1
key_256	11642	1			T1	3		T3	4		T4	7
key_128	589	1			T1	5		T4	2		T9	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14277

1

T1

10

T2

1

T3

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	392	1			T1	2		T4	2		T8	4
enabled	auto[0]	auto[1]	367	1			T1	6		T4	2		T9	1
enabled	auto[1]	auto[0]	575	1			T1	1		T3	4		T4	3
enabled	auto[1]	auto[1]	372	1			T1	1		T2	1		T5	1
disabled	auto[0]	auto[0]	410	1			T4	3		T10	1		T11	1
disabled	auto[0]	auto[1]	434	1			T4	5		T7	2		T10	1
disabled	auto[1]	auto[0]	11312	1			T4	3		T6	194		T7	4
disabled	auto[1]	auto[1]	415	1			T4	4		T7	5		T11	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

1706

1

T1

10

T2

1

T3

4

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

12571

1

T4

15

T6

194

T7

11

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	186	1			T11	1		T12	1		T23	1
key_none	sha2_384	164	1			T4	5		T34	1		T12	4
key_none	sha2_256	172	1			T4	3		T7	1		T12	3
key_1024	sha2_512	195	1			T8	1		T7	2		T11	2
key_1024	sha2_384	171	1			T2	1		T4	1		T7	2
key_512	sha2_512	180	1			T1	1		T4	1		T8	1
key_512	sha2_384	190	1			T4	1		T8	4		T7	3
key_512	sha2_256	171	1			T4	1		T8	1		T7	2
key_384	sha2_512	164	1			T1	1		T5	1		T9	1
key_384	sha2_384	198	1			T5	1		T8	1		T7	1
key_384	sha2_256	180	1			T37	1		T7	1		T12	1
key_256	sha2_512	179	1			T1	1		T4	2		T9	1
key_256	sha2_384	189	1			T4	3		T8	1		T10	2
key_256	sha2_256	11274	1			T1	2		T3	4		T4	2
key_128	sha2_512	209	1			T1	3		T8	1		T10	2
key_128	sha2_384	194	1			T4	2		T9	1		T8	2
key_128	sha2_256	186	1			T1	2		T8	3		T7	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

75

1

T4

1

T23

2

T24

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	186	1			T11	1		T12	1		T23	1
key_none	sha2_384	164	1			T4	5		T34	1		T12	4
key_none	sha2_256	172	1			T4	3		T7	1		T12	3
key_1024	sha2_512	195	1			T8	1		T7	2		T11	2
key_1024	sha2_384	171	1			T2	1		T4	1		T7	2
key_1024	sha2_256	75	1			T4	1		T23	2		T24	1
key_512	sha2_512	180	1			T1	1		T4	1		T8	1
key_512	sha2_384	190	1			T4	1		T8	4		T7	3
key_512	sha2_256	171	1			T4	1		T8	1		T7	2
key_384	sha2_512	164	1			T1	1		T5	1		T9	1
key_384	sha2_384	198	1			T5	1		T8	1		T7	1
key_384	sha2_256	180	1			T37	1		T7	1		T12	1
key_256	sha2_512	179	1			T1	1		T4	2		T9	1
key_256	sha2_384	189	1			T4	3		T8	1		T10	2
key_256	sha2_256	11274	1			T1	2		T3	4		T4	2
key_128	sha2_512	209	1			T1	3		T8	1		T10	2
key_128	sha2_384	194	1			T4	2		T9	1		T8	2
key_128	sha2_256	186	1			T1	2		T8	3		T7	2