Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.86 95.76 94.06 100.00 63.16 91.67 99.49 70.90


Total test records in report: 597
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T515 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3106040074 May 14 01:08:56 PM PDT 24 May 14 01:09:01 PM PDT 24 85141588 ps
T516 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1763262746 May 14 01:09:05 PM PDT 24 May 14 01:09:08 PM PDT 24 37943544 ps
T517 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2879868319 May 14 01:08:41 PM PDT 24 May 14 01:08:47 PM PDT 24 575090475 ps
T518 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3702821320 May 14 01:08:58 PM PDT 24 May 14 01:09:02 PM PDT 24 12476976 ps
T519 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2104655345 May 14 01:09:00 PM PDT 24 May 14 01:09:08 PM PDT 24 151999405 ps
T520 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2000174894 May 14 01:08:55 PM PDT 24 May 14 01:08:59 PM PDT 24 187964522 ps
T521 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1666408045 May 14 01:08:52 PM PDT 24 May 14 01:08:54 PM PDT 24 73539915 ps
T522 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4199245949 May 14 01:08:40 PM PDT 24 May 14 01:08:45 PM PDT 24 150659592 ps
T523 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2329513438 May 14 01:08:55 PM PDT 24 May 14 01:09:01 PM PDT 24 851970471 ps
T524 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3539040042 May 14 01:08:41 PM PDT 24 May 14 01:08:47 PM PDT 24 114196165 ps
T525 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1069508040 May 14 01:08:54 PM PDT 24 May 14 01:08:57 PM PDT 24 15567103 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.619526423 May 14 01:08:40 PM PDT 24 May 14 01:08:42 PM PDT 24 32703959 ps
T526 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1232322509 May 14 01:09:00 PM PDT 24 May 14 01:09:06 PM PDT 24 122743791 ps
T527 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.278879612 May 14 01:08:59 PM PDT 24 May 14 01:09:05 PM PDT 24 490013576 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3229854323 May 14 01:08:40 PM PDT 24 May 14 01:08:45 PM PDT 24 607681602 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1842647420 May 14 01:08:40 PM PDT 24 May 14 01:08:44 PM PDT 24 43575077 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2951610553 May 14 01:08:41 PM PDT 24 May 14 01:08:46 PM PDT 24 195796613 ps
T528 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1544836083 May 14 01:08:37 PM PDT 24 May 14 01:08:39 PM PDT 24 20620288 ps
T529 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2239808898 May 14 01:08:41 PM PDT 24 May 14 01:08:47 PM PDT 24 117965865 ps
T530 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3175198186 May 14 01:08:56 PM PDT 24 May 14 01:09:00 PM PDT 24 58329021 ps
T531 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3594137012 May 14 01:08:58 PM PDT 24 May 14 01:09:02 PM PDT 24 51603785 ps
T98 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1144685424 May 14 01:08:42 PM PDT 24 May 14 01:08:52 PM PDT 24 1329100327 ps
T532 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1184789703 May 14 01:08:55 PM PDT 24 May 14 01:09:00 PM PDT 24 1079139905 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3475691591 May 14 01:08:54 PM PDT 24 May 14 01:08:57 PM PDT 24 29843990 ps
T533 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2346161733 May 14 01:08:58 PM PDT 24 May 14 01:09:03 PM PDT 24 13742466 ps
T534 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2268582622 May 14 01:08:59 PM PDT 24 May 14 01:09:05 PM PDT 24 293957170 ps
T535 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2228729429 May 14 01:08:43 PM PDT 24 May 14 01:08:49 PM PDT 24 389533650 ps
T536 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1400159804 May 14 01:09:07 PM PDT 24 May 14 01:09:09 PM PDT 24 22072962 ps
T537 /workspace/coverage/cover_reg_top/33.hmac_intr_test.4226275103 May 14 01:09:01 PM PDT 24 May 14 01:09:06 PM PDT 24 37142998 ps
T538 /workspace/coverage/cover_reg_top/0.hmac_intr_test.354826215 May 14 01:08:39 PM PDT 24 May 14 01:08:40 PM PDT 24 22208082 ps
T101 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.673721701 May 14 01:08:56 PM PDT 24 May 14 01:08:59 PM PDT 24 104827058 ps
T539 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3651803807 May 14 01:08:59 PM PDT 24 May 14 01:09:05 PM PDT 24 79598684 ps
T540 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3058983064 May 14 01:09:06 PM PDT 24 May 14 01:09:09 PM PDT 24 116390893 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1300882909 May 14 01:08:37 PM PDT 24 May 14 01:08:55 PM PDT 24 1600877501 ps
T541 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3359797693 May 14 01:08:55 PM PDT 24 May 14 01:08:58 PM PDT 24 15284792 ps
T542 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4189650608 May 14 01:08:40 PM PDT 24 May 14 01:08:45 PM PDT 24 433303250 ps
T117 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1235392989 May 14 01:09:00 PM PDT 24 May 14 01:09:06 PM PDT 24 328025654 ps
T543 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2808105414 May 14 01:08:59 PM PDT 24 May 14 01:09:04 PM PDT 24 14001183 ps
T544 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1070336343 May 14 01:09:05 PM PDT 24 May 14 01:09:08 PM PDT 24 45489819 ps
T545 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3327490475 May 14 01:09:01 PM PDT 24 May 14 01:09:06 PM PDT 24 15506393 ps
T546 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2068367487 May 14 01:08:59 PM PDT 24 May 14 01:09:03 PM PDT 24 11599821 ps
T547 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.81317560 May 14 01:08:53 PM PDT 24 May 14 01:08:55 PM PDT 24 126553113 ps
T548 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4269083986 May 14 01:08:53 PM PDT 24 May 14 01:08:56 PM PDT 24 28558607 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1524512740 May 14 01:08:41 PM PDT 24 May 14 01:09:02 PM PDT 24 1592683929 ps
T549 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2122998455 May 14 01:08:57 PM PDT 24 May 14 01:09:03 PM PDT 24 127547746 ps
T119 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1798580126 May 14 01:08:54 PM PDT 24 May 14 01:08:59 PM PDT 24 174979281 ps
T550 /workspace/coverage/cover_reg_top/46.hmac_intr_test.713721819 May 14 01:09:00 PM PDT 24 May 14 01:09:04 PM PDT 24 46239509 ps
T551 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1477847030 May 14 01:08:41 PM PDT 24 May 14 01:08:51 PM PDT 24 474468232 ps
T552 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3424207719 May 14 01:08:41 PM PDT 24 May 14 01:08:50 PM PDT 24 113067834 ps
T120 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1768488244 May 14 01:08:40 PM PDT 24 May 14 01:08:43 PM PDT 24 302734183 ps
T553 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1187806526 May 14 01:08:40 PM PDT 24 May 14 01:08:52 PM PDT 24 1701067906 ps
T121 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.603339284 May 14 01:08:39 PM PDT 24 May 14 01:08:43 PM PDT 24 806638473 ps
T554 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1053508220 May 14 01:08:56 PM PDT 24 May 14 01:09:01 PM PDT 24 326991410 ps
T555 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1147940822 May 14 01:09:01 PM PDT 24 May 14 01:09:06 PM PDT 24 26075317 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2902490960 May 14 01:08:55 PM PDT 24 May 14 01:08:58 PM PDT 24 90947321 ps
T557 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2546298016 May 14 01:08:53 PM PDT 24 May 14 01:08:56 PM PDT 24 284780596 ps
T558 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1922146694 May 14 01:08:37 PM PDT 24 May 14 01:08:55 PM PDT 24 1374995118 ps
T559 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1479632796 May 14 01:08:42 PM PDT 24 May 14 01:08:47 PM PDT 24 184312835 ps
T560 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1928696849 May 14 01:08:58 PM PDT 24 May 14 01:09:02 PM PDT 24 41761585 ps
T561 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.557495826 May 14 01:08:43 PM PDT 24 May 14 01:08:50 PM PDT 24 131690299 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2775648636 May 14 01:08:36 PM PDT 24 May 14 01:08:39 PM PDT 24 53127717 ps
T563 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.110642956 May 14 01:08:56 PM PDT 24 May 14 01:09:01 PM PDT 24 35841363 ps
T564 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.163716369 May 14 01:08:57 PM PDT 24 May 14 01:09:01 PM PDT 24 137278126 ps
T565 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.582145894 May 14 01:08:40 PM PDT 24 May 14 01:08:43 PM PDT 24 37840189 ps
T566 /workspace/coverage/cover_reg_top/6.hmac_intr_test.64310861 May 14 01:08:42 PM PDT 24 May 14 01:08:46 PM PDT 24 35724573 ps
T567 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4019033998 May 14 01:09:01 PM PDT 24 May 14 01:09:09 PM PDT 24 1479872200 ps
T568 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2486677257 May 14 01:08:54 PM PDT 24 May 14 01:08:58 PM PDT 24 81476214 ps
T569 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2743732801 May 14 01:08:59 PM PDT 24 May 14 01:09:04 PM PDT 24 27671029 ps
T570 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1601533689 May 14 01:08:38 PM PDT 24 May 14 01:08:41 PM PDT 24 29859079 ps
T571 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2898087925 May 14 01:08:40 PM PDT 24 May 14 01:08:46 PM PDT 24 3408196357 ps
T572 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2458118686 May 14 01:08:44 PM PDT 24 May 14 01:08:52 PM PDT 24 775218325 ps
T573 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1943545914 May 14 01:08:54 PM PDT 24 May 14 01:08:56 PM PDT 24 41606645 ps
T574 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2762071550 May 14 01:08:41 PM PDT 24 May 14 01:08:46 PM PDT 24 20874063 ps
T122 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1869014379 May 14 01:08:56 PM PDT 24 May 14 01:09:04 PM PDT 24 782150485 ps
T575 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2234100192 May 14 01:08:58 PM PDT 24 May 14 01:09:03 PM PDT 24 86181370 ps
T576 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3857422203 May 14 01:08:57 PM PDT 24 May 14 01:09:03 PM PDT 24 322529441 ps
T577 /workspace/coverage/cover_reg_top/17.hmac_intr_test.649456685 May 14 01:08:59 PM PDT 24 May 14 01:09:03 PM PDT 24 95073002 ps
T578 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3214175191 May 14 01:08:55 PM PDT 24 May 14 01:09:01 PM PDT 24 643405336 ps
T579 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.403885514 May 14 01:08:53 PM PDT 24 May 14 01:08:57 PM PDT 24 55460859 ps
T580 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3131898175 May 14 01:08:42 PM PDT 24 May 14 01:08:47 PM PDT 24 228884664 ps
T581 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4225491297 May 14 01:09:00 PM PDT 24 May 14 01:09:07 PM PDT 24 88894427 ps
T582 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1886597686 May 14 01:08:37 PM PDT 24 May 14 01:08:39 PM PDT 24 29789010 ps
T583 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1575751465 May 14 01:08:55 PM PDT 24 May 14 01:08:59 PM PDT 24 121299047 ps
T584 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3406035376 May 14 01:08:56 PM PDT 24 May 14 01:09:00 PM PDT 24 32125215 ps
T585 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3857182178 May 14 01:08:53 PM PDT 24 May 14 01:08:57 PM PDT 24 2909271568 ps
T586 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.709389372 May 14 01:08:54 PM PDT 24 May 14 01:09:00 PM PDT 24 765743051 ps
T587 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2633690265 May 14 01:08:56 PM PDT 24 May 14 01:09:01 PM PDT 24 206445060 ps
T588 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2896688554 May 14 01:08:39 PM PDT 24 May 14 01:08:41 PM PDT 24 40221954 ps
T589 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2987874344 May 14 01:08:44 PM PDT 24 May 14 01:08:48 PM PDT 24 21083238 ps
T590 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2503058830 May 14 01:08:39 PM PDT 24 May 14 01:08:42 PM PDT 24 175069377 ps
T591 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.646587894 May 14 01:08:45 PM PDT 24 May 14 01:08:49 PM PDT 24 28170616 ps
T592 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3795051470 May 14 01:08:45 PM PDT 24 May 14 01:08:48 PM PDT 24 63093982 ps
T593 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3941837618 May 14 01:08:38 PM PDT 24 May 14 01:08:41 PM PDT 24 144304550 ps
T594 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1980431438 May 14 01:08:59 PM PDT 24 May 14 01:09:04 PM PDT 24 14518842 ps
T595 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2420909035 May 14 01:08:39 PM PDT 24 May 14 01:08:42 PM PDT 24 36450619 ps
T596 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1878901745 May 14 01:08:59 PM PDT 24 May 14 01:09:04 PM PDT 24 46450445 ps
T597 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.828686066 May 14 01:08:56 PM PDT 24 May 14 01:09:02 PM PDT 24 33841221 ps

Test location /workspace/coverage/default/48.hmac_datapath_stress.712603627
Short name T5
Test name
Test status
Simulation time 491701519 ps
CPU time 98.4 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:13:35 PM PDT 24
Peak memory 406572 kb
Host smart-bb7a4c23-3bc7-425c-b193-5d0950feae05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712603627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.712603627
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_smoke.1885224910
Short name T4
Test name
Test status
Simulation time 838168501 ps
CPU time 6.56 seconds
Started May 14 01:10:41 PM PDT 24
Finished May 14 01:10:50 PM PDT 24
Peak memory 200608 kb
Host smart-79e80133-f21a-4b38-b37e-663692e8328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885224910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1885224910
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.2151936158
Short name T29
Test name
Test status
Simulation time 37656148655 ps
CPU time 968.71 seconds
Started May 14 01:12:41 PM PDT 24
Finished May 14 01:28:57 PM PDT 24
Peak memory 758568 kb
Host smart-6409c7df-0675-4596-90ba-d29901e0b01c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151936158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.2151936158
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1014491570
Short name T28
Test name
Test status
Simulation time 309457222 ps
CPU time 0.98 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:21 PM PDT 24
Peak memory 219836 kb
Host smart-ca49aa5a-bfc8-42c4-b1ad-f03b8391c8a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014491570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1014491570
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3848321606
Short name T32
Test name
Test status
Simulation time 1703525565 ps
CPU time 47.93 seconds
Started May 14 01:10:37 PM PDT 24
Finished May 14 01:11:26 PM PDT 24
Peak memory 200660 kb
Host smart-3a5efe42-a042-4c2f-90e6-dd2b7ff7af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848321606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3848321606
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2426770482
Short name T31
Test name
Test status
Simulation time 101106038 ps
CPU time 1.99 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 199956 kb
Host smart-fef4be7c-1bdf-42ac-83f9-211c606f9fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426770482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2426770482
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2647623933
Short name T11
Test name
Test status
Simulation time 653192494 ps
CPU time 18.57 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:09:58 PM PDT 24
Peak memory 218080 kb
Host smart-3e05d80f-f5bf-4a70-8d77-37194630afa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647623933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2647623933
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_error.2549291870
Short name T13
Test name
Test status
Simulation time 11058947300 ps
CPU time 37.61 seconds
Started May 14 01:11:48 PM PDT 24
Finished May 14 01:12:29 PM PDT 24
Peak memory 200740 kb
Host smart-0408b252-6154-49cb-a597-6177596779c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549291870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2549291870
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.4261116436
Short name T6
Test name
Test status
Simulation time 13826461404 ps
CPU time 379.15 seconds
Started May 14 01:10:21 PM PDT 24
Finished May 14 01:16:42 PM PDT 24
Peak memory 200608 kb
Host smart-38b2ac03-e237-4c42-a4ab-8b2cb4a27c86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261116436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.4261116436
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3528158329
Short name T35
Test name
Test status
Simulation time 379011869 ps
CPU time 5.53 seconds
Started May 14 01:10:09 PM PDT 24
Finished May 14 01:10:18 PM PDT 24
Peak memory 200452 kb
Host smart-0a4ad9b2-45b5-47f9-a991-c212a2c3620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528158329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3528158329
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1869014379
Short name T122
Test name
Test status
Simulation time 782150485 ps
CPU time 4.27 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 200256 kb
Host smart-1c440641-ad59-4c15-b8af-007448bbd712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869014379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1869014379
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2386157602
Short name T23
Test name
Test status
Simulation time 14720118035 ps
CPU time 94.24 seconds
Started May 14 01:10:02 PM PDT 24
Finished May 14 01:11:42 PM PDT 24
Peak memory 200812 kb
Host smart-bcc1f07a-b17a-469c-bdef-c66c7a97ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386157602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2386157602
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2242704760
Short name T73
Test name
Test status
Simulation time 247659747425 ps
CPU time 572.14 seconds
Started May 14 01:09:15 PM PDT 24
Finished May 14 01:18:49 PM PDT 24
Peak memory 200752 kb
Host smart-2815f43f-c94a-4020-a86a-8e6f04c0aaad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242704760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2242704760
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3732043248
Short name T103
Test name
Test status
Simulation time 3352807997 ps
CPU time 46.4 seconds
Started May 14 01:09:42 PM PDT 24
Finished May 14 01:10:30 PM PDT 24
Peak memory 200700 kb
Host smart-dac0e360-2df2-411d-aa48-32052f4b2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732043248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3732043248
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3220271350
Short name T21
Test name
Test status
Simulation time 33590921 ps
CPU time 0.58 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:01 PM PDT 24
Peak memory 196016 kb
Host smart-97d2c31f-eb08-4956-84c1-93dbe71e8c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220271350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3220271350
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.882518538
Short name T44
Test name
Test status
Simulation time 261124794 ps
CPU time 17.94 seconds
Started May 14 01:11:49 PM PDT 24
Finished May 14 01:12:10 PM PDT 24
Peak memory 222188 kb
Host smart-e32ab034-216a-44aa-86e4-fd2dd27fbc2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882518538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.882518538
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2825501257
Short name T105
Test name
Test status
Simulation time 3009874955 ps
CPU time 787.83 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:23:00 PM PDT 24
Peak memory 751360 kb
Host smart-4f4c1fc9-5cd0-489a-bdd1-042ca251df9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825501257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2825501257
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4247713957
Short name T109
Test name
Test status
Simulation time 3770193224 ps
CPU time 1119.28 seconds
Started May 14 01:10:24 PM PDT 24
Finished May 14 01:29:05 PM PDT 24
Peak memory 738256 kb
Host smart-ea4fa224-f4ff-4ae2-b457-8b2787c0ac97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247713957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4247713957
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.669716590
Short name T82
Test name
Test status
Simulation time 3287970824 ps
CPU time 66.83 seconds
Started May 14 01:09:16 PM PDT 24
Finished May 14 01:10:24 PM PDT 24
Peak memory 200772 kb
Host smart-23bd1ee1-ffb6-412c-a06f-96c74cb1644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669716590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.669716590
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1300882909
Short name T100
Test name
Test status
Simulation time 1600877501 ps
CPU time 16.79 seconds
Started May 14 01:08:37 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 200012 kb
Host smart-413c1b70-d468-4594-9eaa-445f6ea4f178
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300882909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1300882909
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3214175191
Short name T578
Test name
Test status
Simulation time 643405336 ps
CPU time 3.07 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 200036 kb
Host smart-bf9eddf3-d920-47da-a6f9-c6ab66b65188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214175191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3214175191
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.630638015
Short name T54
Test name
Test status
Simulation time 1794606871 ps
CPU time 4.5 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 200036 kb
Host smart-e5292e20-068f-4dec-abb9-eaff169dacc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630638015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.630638015
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1477847030
Short name T551
Test name
Test status
Simulation time 474468232 ps
CPU time 5.23 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 199964 kb
Host smart-a1a62e50-e5e1-44a5-9d50-92ef9d73380a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477847030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1477847030
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2775648636
Short name T562
Test name
Test status
Simulation time 53127717 ps
CPU time 0.95 seconds
Started May 14 01:08:36 PM PDT 24
Finished May 14 01:08:39 PM PDT 24
Peak memory 199060 kb
Host smart-0767ad82-19e7-4928-a76c-706a7a4e6dd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775648636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2775648636
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3941837618
Short name T593
Test name
Test status
Simulation time 144304550 ps
CPU time 1.71 seconds
Started May 14 01:08:38 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 200108 kb
Host smart-5d850355-1ae8-4f2c-85f7-e269dc661edf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941837618 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3941837618
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1842647420
Short name T95
Test name
Test status
Simulation time 43575077 ps
CPU time 0.98 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:44 PM PDT 24
Peak memory 199872 kb
Host smart-e6a6c8b7-16ff-466f-adcc-76d1d3e6be42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842647420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1842647420
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.354826215
Short name T538
Test name
Test status
Simulation time 22208082 ps
CPU time 0.55 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:40 PM PDT 24
Peak memory 194852 kb
Host smart-8f0f112c-658e-41e6-b44c-15a5f48a0711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354826215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.354826215
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4189650608
Short name T542
Test name
Test status
Simulation time 433303250 ps
CPU time 2.36 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:45 PM PDT 24
Peak memory 200044 kb
Host smart-6434c89d-c36c-413a-8927-3b762ff06b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189650608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4189650608
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.557495826
Short name T561
Test name
Test status
Simulation time 131690299 ps
CPU time 3.68 seconds
Started May 14 01:08:43 PM PDT 24
Finished May 14 01:08:50 PM PDT 24
Peak memory 199996 kb
Host smart-335197ad-a066-41bb-9ff9-f9d317466ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557495826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.557495826
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1768488244
Short name T120
Test name
Test status
Simulation time 302734183 ps
CPU time 1.67 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:43 PM PDT 24
Peak memory 200080 kb
Host smart-af03f5fd-1aac-48ef-a17e-adef726006dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768488244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1768488244
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1187806526
Short name T553
Test name
Test status
Simulation time 1701067906 ps
CPU time 9.18 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:52 PM PDT 24
Peak memory 199572 kb
Host smart-5e89fcd0-c5fb-425f-97a9-0fb9c312a663
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187806526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1187806526
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1922146694
Short name T558
Test name
Test status
Simulation time 1374995118 ps
CPU time 16.83 seconds
Started May 14 01:08:37 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 199972 kb
Host smart-80d63c42-d851-4083-b2c3-81b2f5fedb12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922146694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1922146694
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4125366668
Short name T492
Test name
Test status
Simulation time 78048837 ps
CPU time 0.74 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 198196 kb
Host smart-5eb098f7-5cfa-43bc-a16b-bf89cf8e4359
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125366668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4125366668
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.582145894
Short name T565
Test name
Test status
Simulation time 37840189 ps
CPU time 1.27 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:43 PM PDT 24
Peak memory 199956 kb
Host smart-f6029dfa-4e00-4bdb-b727-39a42872fad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582145894 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.582145894
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1601533689
Short name T570
Test name
Test status
Simulation time 29859079 ps
CPU time 0.85 seconds
Started May 14 01:08:38 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 199392 kb
Host smart-84e11e44-5189-404e-9f76-6a997ae406ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601533689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1601533689
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2831980550
Short name T483
Test name
Test status
Simulation time 42577832 ps
CPU time 0.58 seconds
Started May 14 01:09:02 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194800 kb
Host smart-fe956db6-0196-4194-8d4b-cb56aa4d96c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831980550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2831980550
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4199245949
Short name T522
Test name
Test status
Simulation time 150659592 ps
CPU time 1.67 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:45 PM PDT 24
Peak memory 199996 kb
Host smart-8302cf01-389a-4ffc-8517-4ee09dfe6851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199245949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4199245949
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1216204052
Short name T509
Test name
Test status
Simulation time 85212425 ps
CPU time 1.33 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:44 PM PDT 24
Peak memory 200132 kb
Host smart-1ce3ff3b-7196-46c9-af9a-99215d101f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216204052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1216204052
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2503058830
Short name T590
Test name
Test status
Simulation time 175069377 ps
CPU time 1.8 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:42 PM PDT 24
Peak memory 200044 kb
Host smart-f6e70671-7a47-458b-bbb0-14720dfd6d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503058830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2503058830
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1184789703
Short name T532
Test name
Test status
Simulation time 1079139905 ps
CPU time 2.54 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 200008 kb
Host smart-bb8c2711-0a3b-477a-b428-5c5dcfc4c199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184789703 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1184789703
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3658706239
Short name T486
Test name
Test status
Simulation time 17194714 ps
CPU time 0.76 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 197740 kb
Host smart-30109c00-19d6-4db5-b5a1-d9eb4a819804
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658706239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3658706239
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1943545914
Short name T573
Test name
Test status
Simulation time 41606645 ps
CPU time 0.59 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:56 PM PDT 24
Peak memory 195000 kb
Host smart-22840108-f041-4bf8-850b-7c73a79d3e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943545914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1943545914
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2218637163
Short name T488
Test name
Test status
Simulation time 316658251 ps
CPU time 1.13 seconds
Started May 14 01:08:52 PM PDT 24
Finished May 14 01:08:54 PM PDT 24
Peak memory 199704 kb
Host smart-79af63ff-b41c-438e-9989-573b97b64f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218637163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2218637163
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.46222680
Short name T86
Test name
Test status
Simulation time 192251126 ps
CPU time 3.64 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 200168 kb
Host smart-c96beca2-b2bf-4b1b-b7ed-36cfdbe1a39c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46222680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.46222680
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3857182178
Short name T585
Test name
Test status
Simulation time 2909271568 ps
CPU time 3.21 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 200172 kb
Host smart-8c5f4439-35da-443b-85b1-03fe12c2afbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857182178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3857182178
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1666408045
Short name T521
Test name
Test status
Simulation time 73539915 ps
CPU time 1.18 seconds
Started May 14 01:08:52 PM PDT 24
Finished May 14 01:08:54 PM PDT 24
Peak memory 199904 kb
Host smart-7f383138-257b-4743-9485-ed03c41c6f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666408045 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1666408045
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.635073313
Short name T482
Test name
Test status
Simulation time 16527624 ps
CPU time 0.79 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 198716 kb
Host smart-5cc2c1db-1534-4a0d-aeb8-e8616c423297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635073313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.635073313
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3359797693
Short name T541
Test name
Test status
Simulation time 15284792 ps
CPU time 0.64 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 194872 kb
Host smart-43798416-c8b8-4be2-abfd-35e19b15e5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359797693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3359797693
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1212827996
Short name T511
Test name
Test status
Simulation time 53593405 ps
CPU time 1.3 seconds
Started May 14 01:08:51 PM PDT 24
Finished May 14 01:08:54 PM PDT 24
Peak memory 199556 kb
Host smart-55680967-9ab3-4224-a8f6-bbd2ccb71593
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212827996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1212827996
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2122998455
Short name T549
Test name
Test status
Simulation time 127547746 ps
CPU time 3.33 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 200084 kb
Host smart-9ef75938-3d12-4029-adae-708a5cac4b91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122998455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2122998455
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3857422203
Short name T576
Test name
Test status
Simulation time 322529441 ps
CPU time 2.7 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 200044 kb
Host smart-8430155f-6237-42f6-bab6-78ed4e30e2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857422203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3857422203
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.570274830
Short name T87
Test name
Test status
Simulation time 83622286 ps
CPU time 2.6 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 208272 kb
Host smart-997c9dd9-bf4b-4c85-9b07-3508b5a31181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570274830 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.570274830
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.163716369
Short name T564
Test name
Test status
Simulation time 137278126 ps
CPU time 1.01 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 199628 kb
Host smart-d1f50969-3873-4aa0-a0b2-7517df500c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163716369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.163716369
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3175198186
Short name T530
Test name
Test status
Simulation time 58329021 ps
CPU time 0.62 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 194996 kb
Host smart-b9ecbcd8-6ebf-43e4-aa7d-e0c0e4f8b42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175198186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3175198186
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2003100164
Short name T478
Test name
Test status
Simulation time 201609423 ps
CPU time 1.16 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 198436 kb
Host smart-cea80d3e-e380-4c4b-a02a-6ca642064cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003100164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2003100164
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3469555495
Short name T514
Test name
Test status
Simulation time 224610050 ps
CPU time 1.32 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 200060 kb
Host smart-bce19b6d-2ad3-4477-b773-e1d70e7409f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469555495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3469555495
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.936067883
Short name T497
Test name
Test status
Simulation time 162529410 ps
CPU time 1.69 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 199964 kb
Host smart-ffc21614-dc95-41e7-b31f-da34e6aecf3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936067883 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.936067883
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3475691591
Short name T99
Test name
Test status
Simulation time 29843990 ps
CPU time 0.94 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 199876 kb
Host smart-59565b12-70a1-4e94-9c3f-34436a646658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475691591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3475691591
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4269083986
Short name T548
Test name
Test status
Simulation time 28558607 ps
CPU time 0.66 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:56 PM PDT 24
Peak memory 194952 kb
Host smart-bb895faf-8936-4455-8e71-8281097f7aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269083986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4269083986
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.114037065
Short name T481
Test name
Test status
Simulation time 62196620 ps
CPU time 1.26 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 199712 kb
Host smart-1ecd311d-e60c-4dc5-b7c5-7a4def630894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114037065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.114037065
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3788920536
Short name T57
Test name
Test status
Simulation time 1558607036 ps
CPU time 3.17 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 200120 kb
Host smart-1d6dae36-e579-4f1a-86ec-423ed96f3fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788920536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3788920536
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3910101289
Short name T118
Test name
Test status
Simulation time 230383754 ps
CPU time 4.68 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 199976 kb
Host smart-0d72d3a0-9dae-48a2-b8e5-13409820422b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910101289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3910101289
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2486677257
Short name T568
Test name
Test status
Simulation time 81476214 ps
CPU time 2.69 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 199992 kb
Host smart-c8ecd323-7a87-46de-98f0-b48fa6982025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486677257 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2486677257
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.497905367
Short name T92
Test name
Test status
Simulation time 18133941 ps
CPU time 0.94 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 199564 kb
Host smart-d56d6110-eb1e-467b-907b-02e20ef25b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497905367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.497905367
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1926932753
Short name T504
Test name
Test status
Simulation time 12298727 ps
CPU time 0.58 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 195104 kb
Host smart-57432b7d-7089-4067-a471-491615df5969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926932753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1926932753
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3543837118
Short name T77
Test name
Test status
Simulation time 108687568 ps
CPU time 1.93 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 200084 kb
Host smart-064e4af0-1037-43ee-ac13-e0aa2ba06449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543837118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3543837118
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.676612737
Short name T58
Test name
Test status
Simulation time 76501619 ps
CPU time 1.8 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 200044 kb
Host smart-1197caab-b023-4cca-aa76-145f63b80278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676612737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.676612737
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1235392989
Short name T117
Test name
Test status
Simulation time 328025654 ps
CPU time 2.85 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 199980 kb
Host smart-b5269ce4-16b7-44ea-9c41-d2a038d7e5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235392989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1235392989
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1824878756
Short name T500
Test name
Test status
Simulation time 106464825030 ps
CPU time 566.82 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:18:23 PM PDT 24
Peak memory 215628 kb
Host smart-97ea5da1-1a5b-4cc4-9f8f-8634d7bc3831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824878756 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1824878756
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3406035376
Short name T584
Test name
Test status
Simulation time 32125215 ps
CPU time 0.98 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 199292 kb
Host smart-1ee5ee2c-e472-4ac2-8cab-769eb917dc67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406035376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3406035376
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1861688016
Short name T496
Test name
Test status
Simulation time 12326313 ps
CPU time 0.63 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 194920 kb
Host smart-6cce446f-d253-406e-86ed-2f4284ff5113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861688016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1861688016
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2432725399
Short name T507
Test name
Test status
Simulation time 53875758 ps
CPU time 1.18 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 198472 kb
Host smart-153ba831-ff71-4d42-a8c9-47e12567ecd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432725399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2432725399
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1053508220
Short name T554
Test name
Test status
Simulation time 326991410 ps
CPU time 1.88 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 200032 kb
Host smart-cb220982-e942-4a8f-b396-6d93cbed1eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053508220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1053508220
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.709389372
Short name T586
Test name
Test status
Simulation time 765743051 ps
CPU time 3.28 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 200032 kb
Host smart-5132f964-5411-46af-babe-90cbfd03ed44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709389372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.709389372
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3433567270
Short name T513
Test name
Test status
Simulation time 137529621 ps
CPU time 1.74 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 200112 kb
Host smart-05a05c62-20e4-4e8f-8342-ac42e7eacdf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433567270 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3433567270
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1075456904
Short name T88
Test name
Test status
Simulation time 348953938 ps
CPU time 0.84 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 199532 kb
Host smart-c2025380-60fe-4e10-b477-5690f8b1aac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075456904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1075456904
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.452029062
Short name T489
Test name
Test status
Simulation time 16625750 ps
CPU time 0.64 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 195104 kb
Host smart-f8a848b3-4eef-4e5e-81d9-99567c753d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452029062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.452029062
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3651803807
Short name T539
Test name
Test status
Simulation time 79598684 ps
CPU time 1.18 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 199944 kb
Host smart-619c1d6e-3060-4910-9b61-cc7f03dc4c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651803807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3651803807
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.85666975
Short name T55
Test name
Test status
Simulation time 120797969 ps
CPU time 2.78 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 200176 kb
Host smart-ae74a5dc-e7c3-4b4f-b040-2274bd17daa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85666975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.85666975
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1070336343
Short name T544
Test name
Test status
Simulation time 45489819 ps
CPU time 1.21 seconds
Started May 14 01:09:05 PM PDT 24
Finished May 14 01:09:08 PM PDT 24
Peak memory 200060 kb
Host smart-fb8969b5-7184-4556-a340-6837442609c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070336343 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1070336343
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2831447274
Short name T491
Test name
Test status
Simulation time 25905753 ps
CPU time 0.69 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 197892 kb
Host smart-f6172035-c9e2-4182-b792-3c91ea470504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831447274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2831447274
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.649456685
Short name T577
Test name
Test status
Simulation time 95073002 ps
CPU time 0.59 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 194772 kb
Host smart-e541b761-6ac4-47c4-bf97-7d6023d33463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649456685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.649456685
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.278879612
Short name T527
Test name
Test status
Simulation time 490013576 ps
CPU time 2.39 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 200020 kb
Host smart-a2bacd5b-ff03-4df7-9aa8-c315807c2279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278879612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.278879612
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4019033998
Short name T567
Test name
Test status
Simulation time 1479872200 ps
CPU time 3.42 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:09 PM PDT 24
Peak memory 199964 kb
Host smart-cdbca7c5-6f8a-441a-8c28-200c7a0071a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019033998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4019033998
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1945816835
Short name T115
Test name
Test status
Simulation time 155193015 ps
CPU time 3.07 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 200012 kb
Host smart-71c723f6-6d03-40f6-a1ac-b19ea3ae4a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945816835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1945816835
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1232322509
Short name T526
Test name
Test status
Simulation time 122743791 ps
CPU time 1.88 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 200052 kb
Host smart-53d366d1-2dad-4f2a-8fc8-a83281804035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232322509 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1232322509
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.616765968
Short name T89
Test name
Test status
Simulation time 23199451 ps
CPU time 0.83 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 199164 kb
Host smart-c8174f2e-0a0b-4ae6-a816-37fa98abb7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616765968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.616765968
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.110597439
Short name T75
Test name
Test status
Simulation time 133059969 ps
CPU time 0.61 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194984 kb
Host smart-e3a755ba-1cb3-4198-b879-45b5a233a971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110597439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.110597439
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2268582622
Short name T534
Test name
Test status
Simulation time 293957170 ps
CPU time 2.18 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 199908 kb
Host smart-24fd4800-6fef-4311-86ab-289a70c3c0dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268582622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2268582622
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2104655345
Short name T519
Test name
Test status
Simulation time 151999405 ps
CPU time 3.77 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:08 PM PDT 24
Peak memory 200028 kb
Host smart-21bb3ea3-9a06-44d3-99a2-c5371aee67a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104655345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2104655345
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4233867297
Short name T503
Test name
Test status
Simulation time 51505265 ps
CPU time 1.65 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 200040 kb
Host smart-1c0dc268-20e1-4afb-8c8d-de738046629f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233867297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4233867297
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.585205214
Short name T501
Test name
Test status
Simulation time 113803663 ps
CPU time 1.12 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 199916 kb
Host smart-66a18100-5166-46da-997a-bc53d6597909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585205214 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.585205214
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3327490475
Short name T545
Test name
Test status
Simulation time 15506393 ps
CPU time 0.68 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 198056 kb
Host smart-00fb068e-1038-4572-b12e-d70089b25e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327490475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3327490475
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2346161733
Short name T533
Test name
Test status
Simulation time 13742466 ps
CPU time 0.6 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 194916 kb
Host smart-7097da9a-cd11-4c8f-bcb2-884f57b07f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346161733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2346161733
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.761290700
Short name T61
Test name
Test status
Simulation time 180313460 ps
CPU time 1.72 seconds
Started May 14 01:09:02 PM PDT 24
Finished May 14 01:09:07 PM PDT 24
Peak memory 199968 kb
Host smart-38a13682-2d86-4fed-a838-058d44087c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761290700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.761290700
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1458471540
Short name T30
Test name
Test status
Simulation time 49560597 ps
CPU time 1.5 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 200124 kb
Host smart-b7a34f5a-91cd-4e74-9b16-24cfa5dab4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458471540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1458471540
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4225491297
Short name T581
Test name
Test status
Simulation time 88894427 ps
CPU time 2.79 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:07 PM PDT 24
Peak memory 199992 kb
Host smart-9f7b7b63-c59a-420f-974b-ed632d9899b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225491297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4225491297
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1144685424
Short name T98
Test name
Test status
Simulation time 1329100327 ps
CPU time 6.38 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:52 PM PDT 24
Peak memory 199940 kb
Host smart-74119220-5def-448e-a45f-ddec349286d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144685424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1144685424
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3161466644
Short name T91
Test name
Test status
Simulation time 1227063454 ps
CPU time 14.4 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 199372 kb
Host smart-c3e0a8ed-c53d-4cb4-84b2-418b65a98e3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161466644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3161466644
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2762071550
Short name T574
Test name
Test status
Simulation time 20874063 ps
CPU time 1 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:46 PM PDT 24
Peak memory 199728 kb
Host smart-1c0cd66f-27dc-461c-b3a3-87ec3efc0761
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762071550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2762071550
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2228729429
Short name T535
Test name
Test status
Simulation time 389533650 ps
CPU time 2.31 seconds
Started May 14 01:08:43 PM PDT 24
Finished May 14 01:08:49 PM PDT 24
Peak memory 200044 kb
Host smart-2b4666d6-1f80-4bb8-ba38-9dc52892af51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228729429 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2228729429
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1886597686
Short name T582
Test name
Test status
Simulation time 29789010 ps
CPU time 0.84 seconds
Started May 14 01:08:37 PM PDT 24
Finished May 14 01:08:39 PM PDT 24
Peak memory 199520 kb
Host smart-79e0960a-c8b4-41fd-bfd9-a568678f11bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886597686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1886597686
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.261114742
Short name T484
Test name
Test status
Simulation time 15591937 ps
CPU time 0.58 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 194880 kb
Host smart-abe32361-f9af-489a-bec2-7bf109e05621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261114742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.261114742
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2420909035
Short name T595
Test name
Test status
Simulation time 36450619 ps
CPU time 1.61 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:42 PM PDT 24
Peak memory 199984 kb
Host smart-c0f03bee-a9b2-4366-be25-2ff2fada8cec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420909035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2420909035
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2710448754
Short name T502
Test name
Test status
Simulation time 231850723 ps
CPU time 4.24 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:49 PM PDT 24
Peak memory 200056 kb
Host smart-58192146-6fee-42ee-b9a6-a5dfc346618c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710448754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2710448754
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3478141856
Short name T53
Test name
Test status
Simulation time 493743634 ps
CPU time 3.85 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:45 PM PDT 24
Peak memory 200040 kb
Host smart-3e75bd9f-802c-494c-ae27-765a3cb2b1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478141856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3478141856
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.439363826
Short name T485
Test name
Test status
Simulation time 164125409 ps
CPU time 0.63 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194948 kb
Host smart-3f7eb231-182c-46b5-aa4b-71efd9844a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439363826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.439363826
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1119116988
Short name T495
Test name
Test status
Simulation time 61390577 ps
CPU time 0.62 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194988 kb
Host smart-34db6d85-d115-46f0-ba43-8e473aa4d069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119116988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1119116988
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3670910674
Short name T475
Test name
Test status
Simulation time 38793130 ps
CPU time 0.61 seconds
Started May 14 01:08:57 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 194964 kb
Host smart-1d88dad5-5632-4e08-8525-3635e012b61b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670910674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3670910674
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.674474010
Short name T499
Test name
Test status
Simulation time 12145449 ps
CPU time 0.6 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194908 kb
Host smart-ba31d5cc-b06a-48d2-878c-830dafb5b880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674474010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.674474010
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4253635932
Short name T479
Test name
Test status
Simulation time 11983927 ps
CPU time 0.59 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194924 kb
Host smart-1f9bac61-836b-4cc6-9bcf-5d160dda59be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253635932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4253635932
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2743732801
Short name T569
Test name
Test status
Simulation time 27671029 ps
CPU time 0.61 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 195112 kb
Host smart-b6e45b7e-f6fe-4825-9ff3-1de9210b8c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743732801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2743732801
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3702821320
Short name T518
Test name
Test status
Simulation time 12476976 ps
CPU time 0.64 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 194880 kb
Host smart-795c856b-5283-4cd8-a4bf-6c60109bd875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702821320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3702821320
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4061810667
Short name T508
Test name
Test status
Simulation time 242720864 ps
CPU time 0.6 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 195004 kb
Host smart-03841a85-feb9-4e2d-b028-ab4b420788a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061810667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4061810667
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2304877498
Short name T510
Test name
Test status
Simulation time 28088341 ps
CPU time 0.61 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194596 kb
Host smart-f9e1397b-60f9-4be7-9857-0365c9219309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304877498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2304877498
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.770184640
Short name T477
Test name
Test status
Simulation time 17165873 ps
CPU time 0.61 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 194876 kb
Host smart-dba4dada-b5fe-471e-8c2f-f39b6bd7e545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770184640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.770184640
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3229854323
Short name T94
Test name
Test status
Simulation time 607681602 ps
CPU time 3.51 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:45 PM PDT 24
Peak memory 199944 kb
Host smart-5ea7ade7-abdd-494d-9f01-cf87b89ab086
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229854323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3229854323
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1524512740
Short name T102
Test name
Test status
Simulation time 1592683929 ps
CPU time 17.45 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 199892 kb
Host smart-a2d85f3f-765c-4c4f-9aa9-2de1d38498fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524512740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1524512740
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.646587894
Short name T591
Test name
Test status
Simulation time 28170616 ps
CPU time 0.86 seconds
Started May 14 01:08:45 PM PDT 24
Finished May 14 01:08:49 PM PDT 24
Peak memory 199800 kb
Host smart-04e41f8d-63bf-4a67-bf19-3f864e914eac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646587894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.646587894
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.218085224
Short name T494
Test name
Test status
Simulation time 153371816 ps
CPU time 2.03 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 199972 kb
Host smart-87786a42-ceb5-4b28-b36e-2558ae6d5764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218085224 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.218085224
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.619526423
Short name T93
Test name
Test status
Simulation time 32703959 ps
CPU time 0.71 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:42 PM PDT 24
Peak memory 198056 kb
Host smart-aee3a53e-53fc-416e-b160-a2aa3d54a983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619526423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.619526423
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3795051470
Short name T592
Test name
Test status
Simulation time 63093982 ps
CPU time 0.66 seconds
Started May 14 01:08:45 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 194908 kb
Host smart-1ad9c615-3671-4fb9-bf79-0df3d126e603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795051470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3795051470
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2879868319
Short name T517
Test name
Test status
Simulation time 575090475 ps
CPU time 2.37 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 200020 kb
Host smart-4d94e7e7-347c-4da8-ad41-4313f5cdaba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879868319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2879868319
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2458118686
Short name T572
Test name
Test status
Simulation time 775218325 ps
CPU time 4.55 seconds
Started May 14 01:08:44 PM PDT 24
Finished May 14 01:08:52 PM PDT 24
Peak memory 200052 kb
Host smart-a9b9da3c-1fef-40b6-81b3-8f5850295799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458118686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2458118686
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2611909624
Short name T123
Test name
Test status
Simulation time 902523249 ps
CPU time 4.31 seconds
Started May 14 01:08:43 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 199988 kb
Host smart-84333c5c-543d-49c0-a688-1d89abd81076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611909624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2611909624
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1763262746
Short name T516
Test name
Test status
Simulation time 37943544 ps
CPU time 0.58 seconds
Started May 14 01:09:05 PM PDT 24
Finished May 14 01:09:08 PM PDT 24
Peak memory 194948 kb
Host smart-39a1f334-3ecd-4853-8841-e175361144d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763262746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1763262746
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3333623107
Short name T490
Test name
Test status
Simulation time 44272527 ps
CPU time 0.58 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194880 kb
Host smart-7fbb7819-f8d5-4d54-8cfb-cbf411b00e42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333623107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3333623107
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3058983064
Short name T540
Test name
Test status
Simulation time 116390893 ps
CPU time 0.6 seconds
Started May 14 01:09:06 PM PDT 24
Finished May 14 01:09:09 PM PDT 24
Peak memory 194936 kb
Host smart-700c0fb4-fcd4-4ff0-b90c-bfe901bcb098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058983064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3058983064
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.4226275103
Short name T537
Test name
Test status
Simulation time 37142998 ps
CPU time 0.62 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194880 kb
Host smart-00c2793c-b4be-4534-b936-9b4a69722de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226275103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.4226275103
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2345517716
Short name T74
Test name
Test status
Simulation time 19177861 ps
CPU time 0.58 seconds
Started May 14 01:09:05 PM PDT 24
Finished May 14 01:09:08 PM PDT 24
Peak memory 194900 kb
Host smart-1d6a827d-bcd6-4338-91e1-7d8ff1a86bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345517716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2345517716
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1878901745
Short name T596
Test name
Test status
Simulation time 46450445 ps
CPU time 0.61 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194840 kb
Host smart-8f8a65e9-7f19-4f10-8d8b-bca8e817ca3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878901745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1878901745
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2068367487
Short name T546
Test name
Test status
Simulation time 11599821 ps
CPU time 0.6 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 194924 kb
Host smart-9dd6291c-18b0-4a44-8662-2b067fd5d17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068367487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2068367487
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1928696849
Short name T560
Test name
Test status
Simulation time 41761585 ps
CPU time 0.61 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 194840 kb
Host smart-c1437b82-e4e3-4594-a9cc-df1deeac91e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928696849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1928696849
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.653491326
Short name T506
Test name
Test status
Simulation time 39578415 ps
CPU time 0.64 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 194996 kb
Host smart-b8435233-74d9-4b3d-a228-f50c3c7ef925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653491326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.653491326
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1980431438
Short name T594
Test name
Test status
Simulation time 14518842 ps
CPU time 0.62 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194968 kb
Host smart-1a6d5875-7e96-4a36-8812-873222720830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980431438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1980431438
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3424207719
Short name T552
Test name
Test status
Simulation time 113067834 ps
CPU time 5.72 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:50 PM PDT 24
Peak memory 199308 kb
Host smart-8ddae5da-3eb8-47f0-a5a0-cd56b10e7ff9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424207719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3424207719
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3344536649
Short name T97
Test name
Test status
Simulation time 831403991 ps
CPU time 9.43 seconds
Started May 14 01:08:44 PM PDT 24
Finished May 14 01:08:56 PM PDT 24
Peak memory 199024 kb
Host smart-6aa0a687-6dc0-4a93-8405-76bdac9f9fa6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344536649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3344536649
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2951610553
Short name T96
Test name
Test status
Simulation time 195796613 ps
CPU time 0.83 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:46 PM PDT 24
Peak memory 198944 kb
Host smart-d6cd7234-1bf5-4f15-98c0-e52710c567ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951610553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2951610553
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.534208950
Short name T56
Test name
Test status
Simulation time 242366035862 ps
CPU time 992.77 seconds
Started May 14 01:08:44 PM PDT 24
Finished May 14 01:25:20 PM PDT 24
Peak memory 216588 kb
Host smart-95e80127-8213-427b-a90a-97e173651df5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534208950 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.534208950
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1544836083
Short name T528
Test name
Test status
Simulation time 20620288 ps
CPU time 0.68 seconds
Started May 14 01:08:37 PM PDT 24
Finished May 14 01:08:39 PM PDT 24
Peak memory 197284 kb
Host smart-c07b5978-22fc-44a9-b3f5-ddb9d0fc6728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544836083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1544836083
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3865358556
Short name T512
Test name
Test status
Simulation time 46051344 ps
CPU time 0.67 seconds
Started May 14 01:08:44 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 194876 kb
Host smart-c90b46f9-fcbd-46ae-b27d-5e6329ebf707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865358556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3865358556
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2239808898
Short name T529
Test name
Test status
Simulation time 117965865 ps
CPU time 2.48 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 199788 kb
Host smart-72a31136-eb23-4861-b4eb-e2bc49551128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239808898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2239808898
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3131898175
Short name T580
Test name
Test status
Simulation time 228884664 ps
CPU time 1.51 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 200116 kb
Host smart-492f89ca-9f9a-45bb-88c5-fe98a5ac21fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131898175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3131898175
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.603339284
Short name T121
Test name
Test status
Simulation time 806638473 ps
CPU time 2.89 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:43 PM PDT 24
Peak memory 200028 kb
Host smart-387a219a-d2c5-4a12-b2c9-4a152fbbb0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603339284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.603339284
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3594137012
Short name T531
Test name
Test status
Simulation time 51603785 ps
CPU time 0.68 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 194924 kb
Host smart-9c4601b9-6987-4fa5-875d-0ffd1ab430a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594137012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3594137012
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3906024311
Short name T487
Test name
Test status
Simulation time 128119650 ps
CPU time 0.66 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194940 kb
Host smart-cdd3a2a3-91f9-4985-bd4f-21dd5a892b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906024311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3906024311
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2234100192
Short name T575
Test name
Test status
Simulation time 86181370 ps
CPU time 0.61 seconds
Started May 14 01:08:58 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 194768 kb
Host smart-25644f7d-d10d-4745-9c8d-e4a1adc02e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234100192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2234100192
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2715179760
Short name T480
Test name
Test status
Simulation time 19037921 ps
CPU time 0.63 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194976 kb
Host smart-078fbe8e-5f42-4c92-844e-19701dad56a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715179760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2715179760
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2808105414
Short name T543
Test name
Test status
Simulation time 14001183 ps
CPU time 0.59 seconds
Started May 14 01:08:59 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194964 kb
Host smart-160cf39e-dd6b-4efa-b465-9a84af451c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808105414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2808105414
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1147940822
Short name T555
Test name
Test status
Simulation time 26075317 ps
CPU time 0.65 seconds
Started May 14 01:09:01 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 194688 kb
Host smart-30369e42-f017-48ff-8df3-dd30c10cabc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147940822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1147940822
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.713721819
Short name T550
Test name
Test status
Simulation time 46239509 ps
CPU time 0.64 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194928 kb
Host smart-bdb76560-c06d-42b2-bf7f-539fc9f0ff04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713721819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.713721819
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1400159804
Short name T536
Test name
Test status
Simulation time 22072962 ps
CPU time 0.59 seconds
Started May 14 01:09:07 PM PDT 24
Finished May 14 01:09:09 PM PDT 24
Peak memory 194964 kb
Host smart-08749022-c8a3-413e-8e14-f6ddea842e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400159804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1400159804
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2065743283
Short name T493
Test name
Test status
Simulation time 13504025 ps
CPU time 0.56 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 194796 kb
Host smart-5edac949-daf5-4823-b570-d184fc8131e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065743283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2065743283
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1701755385
Short name T76
Test name
Test status
Simulation time 109618528 ps
CPU time 0.6 seconds
Started May 14 01:09:00 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 194904 kb
Host smart-dd08ca1c-38b2-4c6d-ba39-2587a4911593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701755385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1701755385
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1828430574
Short name T505
Test name
Test status
Simulation time 49439269 ps
CPU time 3.16 seconds
Started May 14 01:08:45 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 208256 kb
Host smart-9d07257c-4b36-43aa-add9-fc8895bb6f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828430574 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1828430574
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2896688554
Short name T588
Test name
Test status
Simulation time 40221954 ps
CPU time 0.79 seconds
Started May 14 01:08:39 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 199416 kb
Host smart-572161a0-c674-4f14-9206-e10f15700384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896688554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2896688554
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.730815214
Short name T498
Test name
Test status
Simulation time 22681909 ps
CPU time 0.6 seconds
Started May 14 01:08:43 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 194884 kb
Host smart-eb0a8930-5c24-48e9-871a-972dbf8d3bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730815214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.730815214
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3539040042
Short name T524
Test name
Test status
Simulation time 114196165 ps
CPU time 2.38 seconds
Started May 14 01:08:41 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 199764 kb
Host smart-de2ca3be-cd70-4b2e-abf5-08629fac8ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539040042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3539040042
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1668706989
Short name T52
Test name
Test status
Simulation time 148440995 ps
CPU time 1.95 seconds
Started May 14 01:08:43 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 200152 kb
Host smart-b11d7944-4dda-43d6-8ee5-719edad43f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668706989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1668706989
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2084966884
Short name T116
Test name
Test status
Simulation time 158288383 ps
CPU time 3.14 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:49 PM PDT 24
Peak memory 199980 kb
Host smart-714ff648-8957-4076-8a01-d0b4b9680d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084966884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2084966884
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2000174894
Short name T520
Test name
Test status
Simulation time 187964522 ps
CPU time 1.36 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 199916 kb
Host smart-1c8e3729-af7c-4e85-8b0a-dd6051e7cf3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000174894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2000174894
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2987874344
Short name T589
Test name
Test status
Simulation time 21083238 ps
CPU time 0.72 seconds
Started May 14 01:08:44 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 197920 kb
Host smart-625864d1-8340-451a-97a2-5245c0610be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987874344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2987874344
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.64310861
Short name T566
Test name
Test status
Simulation time 35724573 ps
CPU time 0.59 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:46 PM PDT 24
Peak memory 194788 kb
Host smart-b080d59b-6fad-4719-a6b9-1de2319c3eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64310861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.64310861
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2633690265
Short name T587
Test name
Test status
Simulation time 206445060 ps
CPU time 1.22 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 199656 kb
Host smart-27e81fef-f0ce-4b52-bfc3-7e16f7cf96e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633690265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2633690265
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2898087925
Short name T571
Test name
Test status
Simulation time 3408196357 ps
CPU time 3.82 seconds
Started May 14 01:08:40 PM PDT 24
Finished May 14 01:08:46 PM PDT 24
Peak memory 200108 kb
Host smart-b167847b-d59e-43a3-8a48-c27b13a0d6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898087925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2898087925
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1479632796
Short name T559
Test name
Test status
Simulation time 184312835 ps
CPU time 1.71 seconds
Started May 14 01:08:42 PM PDT 24
Finished May 14 01:08:47 PM PDT 24
Peak memory 199928 kb
Host smart-3c47a8da-5ac2-4b89-a3e3-afc05f5f48f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479632796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1479632796
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3113137687
Short name T59
Test name
Test status
Simulation time 18198766856 ps
CPU time 175.94 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:11:50 PM PDT 24
Peak memory 215800 kb
Host smart-1134382c-c5d7-40d9-8131-2482dd036344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113137687 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3113137687
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.81317560
Short name T547
Test name
Test status
Simulation time 126553113 ps
CPU time 0.95 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 199328 kb
Host smart-d973a423-5eb4-43ff-93d2-944f6eaf5f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81317560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.81317560
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2902490960
Short name T556
Test name
Test status
Simulation time 90947321 ps
CPU time 0.61 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 194868 kb
Host smart-b3d85453-2e59-42de-9984-d92352bd0b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902490960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2902490960
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2188771171
Short name T60
Test name
Test status
Simulation time 124534248 ps
CPU time 1.74 seconds
Started May 14 01:08:52 PM PDT 24
Finished May 14 01:08:54 PM PDT 24
Peak memory 199268 kb
Host smart-09bd7c7d-ed60-4673-9bb6-1d491527c49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188771171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2188771171
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.828686066
Short name T597
Test name
Test status
Simulation time 33841221 ps
CPU time 1.78 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 200036 kb
Host smart-86ff4a55-27df-40f2-8b32-de2700861929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828686066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.828686066
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1798580126
Short name T119
Test name
Test status
Simulation time 174979281 ps
CPU time 3.16 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 200008 kb
Host smart-43d9362e-9367-41f0-9e92-b620f0d112af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798580126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1798580126
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2546298016
Short name T557
Test name
Test status
Simulation time 284780596 ps
CPU time 1.77 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:56 PM PDT 24
Peak memory 200032 kb
Host smart-20cc656d-1a2f-49c9-976a-97d7d7f0aa67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546298016 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2546298016
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.878262250
Short name T90
Test name
Test status
Simulation time 26534261 ps
CPU time 0.87 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 199444 kb
Host smart-80bde7e0-27e8-49fd-bf11-f2e0ed362089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878262250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.878262250
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1069508040
Short name T525
Test name
Test status
Simulation time 15567103 ps
CPU time 0.66 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 194884 kb
Host smart-333169e7-b914-45ad-9941-2dc47e3896e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069508040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1069508040
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1575751465
Short name T583
Test name
Test status
Simulation time 121299047 ps
CPU time 2.41 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 200008 kb
Host smart-247b4dee-5598-4e74-90e7-88de911f0628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575751465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1575751465
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2329513438
Short name T523
Test name
Test status
Simulation time 851970471 ps
CPU time 3.35 seconds
Started May 14 01:08:55 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 200056 kb
Host smart-6f550689-826a-466c-92ac-7c282f8e0db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329513438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2329513438
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.110642956
Short name T563
Test name
Test status
Simulation time 35841363 ps
CPU time 1.22 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 199840 kb
Host smart-ca201288-d65c-45ed-8aba-f93a95b77a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110642956 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.110642956
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.673721701
Short name T101
Test name
Test status
Simulation time 104827058 ps
CPU time 0.81 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 199404 kb
Host smart-b0e7a5c2-e477-423d-9bde-b6c21bd72363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673721701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.673721701
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4162566268
Short name T476
Test name
Test status
Simulation time 18436489 ps
CPU time 0.7 seconds
Started May 14 01:08:54 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 194900 kb
Host smart-1742a2cf-a389-480b-894a-276bd0bc2afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162566268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4162566268
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3106040074
Short name T515
Test name
Test status
Simulation time 85141588 ps
CPU time 1.11 seconds
Started May 14 01:08:56 PM PDT 24
Finished May 14 01:09:01 PM PDT 24
Peak memory 198468 kb
Host smart-72d60da3-da2d-40a9-863d-5cb99133943b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106040074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3106040074
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.403885514
Short name T579
Test name
Test status
Simulation time 55460859 ps
CPU time 2.69 seconds
Started May 14 01:08:53 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 200112 kb
Host smart-6e988061-8c82-4378-87ad-d740688b2f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403885514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.403885514
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1328187586
Short name T364
Test name
Test status
Simulation time 55414316 ps
CPU time 0.58 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:09:14 PM PDT 24
Peak memory 196316 kb
Host smart-c95e9446-5cc2-4c19-b58a-841236f82dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328187586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1328187586
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2204012287
Short name T456
Test name
Test status
Simulation time 897868574 ps
CPU time 52.31 seconds
Started May 14 01:09:09 PM PDT 24
Finished May 14 01:10:03 PM PDT 24
Peak memory 233452 kb
Host smart-90b42adc-7091-4b97-ad91-9a843d898fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204012287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2204012287
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2606049039
Short name T239
Test name
Test status
Simulation time 1339264674 ps
CPU time 33.85 seconds
Started May 14 01:09:12 PM PDT 24
Finished May 14 01:09:48 PM PDT 24
Peak memory 200608 kb
Host smart-f2614f20-442c-4259-9cf3-1303282867eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606049039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2606049039
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1740351745
Short name T395
Test name
Test status
Simulation time 4623332374 ps
CPU time 597.5 seconds
Started May 14 01:09:06 PM PDT 24
Finished May 14 01:19:06 PM PDT 24
Peak memory 704660 kb
Host smart-c5b8c5f3-d6ad-4739-a4c9-b96c4db5b367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740351745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1740351745
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2107616297
Short name T246
Test name
Test status
Simulation time 2627582385 ps
CPU time 19.74 seconds
Started May 14 01:09:08 PM PDT 24
Finished May 14 01:09:29 PM PDT 24
Peak memory 200732 kb
Host smart-11b278af-a5bd-4c99-a285-80a64fee710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107616297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2107616297
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1342825238
Short name T39
Test name
Test status
Simulation time 96685454 ps
CPU time 1.05 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:09:15 PM PDT 24
Peak memory 219956 kb
Host smart-726dcf65-e1d8-49c8-9fe4-5a07e2ab9cd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342825238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1342825238
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3042950550
Short name T210
Test name
Test status
Simulation time 457704934 ps
CPU time 6.24 seconds
Started May 14 01:09:06 PM PDT 24
Finished May 14 01:09:14 PM PDT 24
Peak memory 200588 kb
Host smart-50235067-84e5-46db-9d3c-f275294f48df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042950550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3042950550
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.742759659
Short name T143
Test name
Test status
Simulation time 54894066 ps
CPU time 1.08 seconds
Started May 14 01:09:12 PM PDT 24
Finished May 14 01:09:16 PM PDT 24
Peak memory 200336 kb
Host smart-f71ee0c9-507f-48ed-b760-b05a8256c510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742759659 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.742759659
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3568171627
Short name T242
Test name
Test status
Simulation time 28364734380 ps
CPU time 419.45 seconds
Started May 14 01:09:14 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 200692 kb
Host smart-3aa09888-b3a2-4678-b12e-34d044d8eeb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568171627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3568171627
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1668692234
Short name T185
Test name
Test status
Simulation time 12982193 ps
CPU time 0.56 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:09:13 PM PDT 24
Peak memory 196052 kb
Host smart-d0a33138-530d-4905-ba87-0838274d8a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668692234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1668692234
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3067017856
Short name T346
Test name
Test status
Simulation time 8211315245 ps
CPU time 37.49 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:58 PM PDT 24
Peak memory 221768 kb
Host smart-b9995807-151a-47e1-be21-f448ff69a588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067017856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3067017856
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2141294175
Short name T236
Test name
Test status
Simulation time 1048072166 ps
CPU time 42.3 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:09:56 PM PDT 24
Peak memory 200576 kb
Host smart-a9f1b147-982a-4c8e-a74b-bf6497548e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141294175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2141294175
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.503400413
Short name T442
Test name
Test status
Simulation time 6465171486 ps
CPU time 404.66 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 646208 kb
Host smart-4097abde-e0c1-4c5e-bfb8-91d4df4a0c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503400413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.503400413
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4247639582
Short name T253
Test name
Test status
Simulation time 4652434608 ps
CPU time 82.47 seconds
Started May 14 01:09:13 PM PDT 24
Finished May 14 01:10:38 PM PDT 24
Peak memory 200736 kb
Host smart-d4a8b057-5027-43bc-b7af-97e38a47cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247639582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4247639582
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2997095868
Short name T343
Test name
Test status
Simulation time 108947503 ps
CPU time 2.03 seconds
Started May 14 01:09:13 PM PDT 24
Finished May 14 01:09:18 PM PDT 24
Peak memory 200568 kb
Host smart-d24f1a39-6d44-4dca-8463-2ddaa91dc555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997095868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2997095868
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.310105062
Short name T382
Test name
Test status
Simulation time 75955793 ps
CPU time 1.18 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:09:14 PM PDT 24
Peak memory 199728 kb
Host smart-95493668-218f-452a-87f4-5dacda8f73f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310105062 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.310105062
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1838553821
Short name T434
Test name
Test status
Simulation time 65243837009 ps
CPU time 472.45 seconds
Started May 14 01:09:13 PM PDT 24
Finished May 14 01:17:08 PM PDT 24
Peak memory 200584 kb
Host smart-3f169e73-99d0-494d-b2ad-6cfcb76577c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838553821 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1838553821
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.566326091
Short name T419
Test name
Test status
Simulation time 18166830 ps
CPU time 0.56 seconds
Started May 14 01:09:51 PM PDT 24
Finished May 14 01:09:54 PM PDT 24
Peak memory 195372 kb
Host smart-563dd57d-305b-4389-bc87-ea52e0dcd305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566326091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.566326091
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3276568134
Short name T467
Test name
Test status
Simulation time 1965083940 ps
CPU time 56.57 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:10:48 PM PDT 24
Peak memory 230192 kb
Host smart-f7a416e8-651c-49d0-af7f-6e36ca24bc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276568134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3276568134
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.624034870
Short name T315
Test name
Test status
Simulation time 1726526226 ps
CPU time 46.61 seconds
Started May 14 01:09:53 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 200596 kb
Host smart-c673a385-7780-45c9-b770-7e41c54036a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624034870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.624034870
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.396169465
Short name T66
Test name
Test status
Simulation time 1933968369 ps
CPU time 650.21 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:20:40 PM PDT 24
Peak memory 707628 kb
Host smart-a9924b39-0036-429c-bc1d-25fc1f08d74d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396169465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.396169465
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2288987625
Short name T390
Test name
Test status
Simulation time 1837893357 ps
CPU time 5.07 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:09:55 PM PDT 24
Peak memory 200652 kb
Host smart-3515fc91-1fd8-44a4-9303-d0e27fb19167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288987625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2288987625
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.576656618
Short name T267
Test name
Test status
Simulation time 584028889 ps
CPU time 5.09 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:09:57 PM PDT 24
Peak memory 200584 kb
Host smart-217b2a53-c54a-4947-aedd-68613ebf92eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576656618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.576656618
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2437607717
Short name T333
Test name
Test status
Simulation time 73357019 ps
CPU time 1.35 seconds
Started May 14 01:09:54 PM PDT 24
Finished May 14 01:09:59 PM PDT 24
Peak memory 200600 kb
Host smart-5db4ea7e-c751-4ff0-999a-8c8345b1ee98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437607717 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2437607717
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3423933088
Short name T417
Test name
Test status
Simulation time 35990402496 ps
CPU time 481.45 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:17:53 PM PDT 24
Peak memory 200640 kb
Host smart-af9cb4db-a251-4421-91c4-2218cdfcd5bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423933088 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3423933088
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1592377370
Short name T193
Test name
Test status
Simulation time 32740137 ps
CPU time 0.58 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:01 PM PDT 24
Peak memory 196096 kb
Host smart-cd6b585d-905b-4b68-ae11-bbfb64def3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592377370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1592377370
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2230461768
Short name T286
Test name
Test status
Simulation time 3965351622 ps
CPU time 64.79 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:10:56 PM PDT 24
Peak memory 222908 kb
Host smart-77752827-250b-451c-9561-12a7454569fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230461768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2230461768
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2466115770
Short name T380
Test name
Test status
Simulation time 18780607 ps
CPU time 0.63 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:09:50 PM PDT 24
Peak memory 196792 kb
Host smart-f2ff5417-30e2-4bd3-8e41-c83c655591d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466115770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2466115770
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2229485636
Short name T215
Test name
Test status
Simulation time 1163687879 ps
CPU time 82.6 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:11:13 PM PDT 24
Peak memory 459608 kb
Host smart-71e7d45e-6f77-4510-ae3a-72d92ae4b497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229485636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2229485636
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.94403161
Short name T176
Test name
Test status
Simulation time 11617714476 ps
CPU time 103.55 seconds
Started May 14 01:09:51 PM PDT 24
Finished May 14 01:11:38 PM PDT 24
Peak memory 200744 kb
Host smart-7c1e8861-291d-454e-a930-6e18424d493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94403161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.94403161
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2902355522
Short name T164
Test name
Test status
Simulation time 212217638 ps
CPU time 6.68 seconds
Started May 14 01:09:54 PM PDT 24
Finished May 14 01:10:04 PM PDT 24
Peak memory 200676 kb
Host smart-5a6c0f77-2a2b-4ec1-81f4-22baa634b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902355522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2902355522
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2613716837
Short name T71
Test name
Test status
Simulation time 173742187298 ps
CPU time 1251.58 seconds
Started May 14 01:09:50 PM PDT 24
Finished May 14 01:30:44 PM PDT 24
Peak memory 332648 kb
Host smart-bdf4ff21-2280-492c-9686-54b939b38854
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613716837 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2613716837
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3264909381
Short name T351
Test name
Test status
Simulation time 145012353 ps
CPU time 1.03 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 200192 kb
Host smart-506d0446-1224-42f9-b0c2-96e8c2425c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264909381 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3264909381
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1114884020
Short name T159
Test name
Test status
Simulation time 50248522416 ps
CPU time 547.01 seconds
Started May 14 01:09:52 PM PDT 24
Finished May 14 01:19:02 PM PDT 24
Peak memory 200696 kb
Host smart-1d492253-f49a-4517-8afd-dc3a0238c8f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114884020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1114884020
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1198818301
Short name T433
Test name
Test status
Simulation time 44342143 ps
CPU time 0.57 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:09:51 PM PDT 24
Peak memory 196368 kb
Host smart-b91472ca-aeae-4095-91b8-8cfdda03fb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198818301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1198818301
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1320849895
Short name T464
Test name
Test status
Simulation time 1749617256 ps
CPU time 62.01 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:10:51 PM PDT 24
Peak memory 241592 kb
Host smart-2c68c010-18bb-4a24-9727-abf800dea556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320849895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1320849895
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4195267798
Short name T383
Test name
Test status
Simulation time 10572759481 ps
CPU time 39.4 seconds
Started May 14 01:09:48 PM PDT 24
Finished May 14 01:10:30 PM PDT 24
Peak memory 200676 kb
Host smart-ecf2d27f-f582-4a20-9ebf-e4d4c36b535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195267798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4195267798
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2637941290
Short name T316
Test name
Test status
Simulation time 878409283 ps
CPU time 223.68 seconds
Started May 14 01:10:12 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 598640 kb
Host smart-3ea71479-8b81-45ac-8812-4c92f41315eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637941290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2637941290
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2225848855
Short name T389
Test name
Test status
Simulation time 6858494395 ps
CPU time 55.39 seconds
Started May 14 01:10:03 PM PDT 24
Finished May 14 01:11:04 PM PDT 24
Peak memory 200668 kb
Host smart-b8717c15-336d-4182-b6c2-16c1a21a3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225848855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2225848855
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2052712485
Short name T238
Test name
Test status
Simulation time 133736741 ps
CPU time 2.64 seconds
Started May 14 01:09:52 PM PDT 24
Finished May 14 01:09:57 PM PDT 24
Peak memory 200656 kb
Host smart-7bd74d03-90e3-48e0-b71e-ebd34cbbb361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052712485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2052712485
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.620036099
Short name T354
Test name
Test status
Simulation time 287512168 ps
CPU time 1.41 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 200448 kb
Host smart-ba1756e3-c884-4432-a703-38c4610e1e8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620036099 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.620036099
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3596940407
Short name T443
Test name
Test status
Simulation time 105598989947 ps
CPU time 469.19 seconds
Started May 14 01:09:56 PM PDT 24
Finished May 14 01:17:49 PM PDT 24
Peak memory 200588 kb
Host smart-0f999496-f293-45cd-99fa-46b0814e8a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596940407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3596940407
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.794686377
Short name T127
Test name
Test status
Simulation time 471620740 ps
CPU time 21.62 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:10:13 PM PDT 24
Peak memory 216836 kb
Host smart-8dcd8ee0-0268-4c05-b8cb-99361b5137ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794686377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.794686377
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1310956104
Short name T345
Test name
Test status
Simulation time 1871256482 ps
CPU time 50.46 seconds
Started May 14 01:09:51 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 200636 kb
Host smart-ae30104d-a107-4f71-9d8c-bd0a9f27efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310956104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1310956104
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1260226253
Short name T335
Test name
Test status
Simulation time 8571846181 ps
CPU time 117.09 seconds
Started May 14 01:09:58 PM PDT 24
Finished May 14 01:11:59 PM PDT 24
Peak memory 200688 kb
Host smart-6173af42-0f79-4f5b-b89e-0179d854011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260226253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1260226253
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3138735606
Short name T261
Test name
Test status
Simulation time 117161233 ps
CPU time 1.21 seconds
Started May 14 01:10:02 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 200504 kb
Host smart-3b666d10-d880-41da-92bc-d026c44e176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138735606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3138735606
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.514112122
Short name T139
Test name
Test status
Simulation time 44609992 ps
CPU time 1.06 seconds
Started May 14 01:09:53 PM PDT 24
Finished May 14 01:09:58 PM PDT 24
Peak memory 200048 kb
Host smart-63da6a72-d6cb-4035-9e76-c055bf595dc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514112122 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.514112122
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3457091055
Short name T189
Test name
Test status
Simulation time 33224268029 ps
CPU time 475.53 seconds
Started May 14 01:09:52 PM PDT 24
Finished May 14 01:17:51 PM PDT 24
Peak memory 200612 kb
Host smart-b67c9a16-b2be-4628-bf13-969d26f2661b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457091055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3457091055
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1950844875
Short name T199
Test name
Test status
Simulation time 30459318 ps
CPU time 0.57 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:01 PM PDT 24
Peak memory 196020 kb
Host smart-8c19bdc8-b20e-4c51-afec-308ac934cc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950844875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1950844875
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2205641618
Short name T266
Test name
Test status
Simulation time 1107582521 ps
CPU time 56.27 seconds
Started May 14 01:10:07 PM PDT 24
Finished May 14 01:11:07 PM PDT 24
Peak memory 227040 kb
Host smart-d0aca7ee-41a3-4c29-82c1-29c6040cde9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205641618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2205641618
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3339913848
Short name T377
Test name
Test status
Simulation time 10661531090 ps
CPU time 32 seconds
Started May 14 01:09:42 PM PDT 24
Finished May 14 01:10:16 PM PDT 24
Peak memory 200740 kb
Host smart-294099d4-07c7-468c-858f-1204bbd02f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339913848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3339913848
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.654040144
Short name T393
Test name
Test status
Simulation time 214509945 ps
CPU time 0.85 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:09:51 PM PDT 24
Peak memory 198836 kb
Host smart-37fbb236-5fe2-41c8-969d-910ae910fc08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654040144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.654040144
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.94594723
Short name T245
Test name
Test status
Simulation time 11140230493 ps
CPU time 51.2 seconds
Started May 14 01:09:58 PM PDT 24
Finished May 14 01:10:52 PM PDT 24
Peak memory 200688 kb
Host smart-f9f449ca-9a49-43a3-9cd4-10465b1e1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94594723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.94594723
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4052311454
Short name T79
Test name
Test status
Simulation time 276800831 ps
CPU time 2.36 seconds
Started May 14 01:09:52 PM PDT 24
Finished May 14 01:09:58 PM PDT 24
Peak memory 200644 kb
Host smart-3028b129-250f-46b1-9a81-ecce3b211601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052311454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4052311454
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1303763758
Short name T186
Test name
Test status
Simulation time 273466327 ps
CPU time 1.28 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:07 PM PDT 24
Peak memory 200608 kb
Host smart-42708f22-c8a2-46a9-b697-c52e5f2d6adf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303763758 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1303763758
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2744302804
Short name T466
Test name
Test status
Simulation time 134124886804 ps
CPU time 500.68 seconds
Started May 14 01:09:53 PM PDT 24
Finished May 14 01:18:17 PM PDT 24
Peak memory 200624 kb
Host smart-a7511935-e8d8-4c0e-b0e5-39d85ca4168b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744302804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2744302804
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_alert_test.865734315
Short name T355
Test name
Test status
Simulation time 13819630 ps
CPU time 0.6 seconds
Started May 14 01:10:10 PM PDT 24
Finished May 14 01:10:13 PM PDT 24
Peak memory 196404 kb
Host smart-b2073537-05c6-4952-99ab-0e03062c9d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865734315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.865734315
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4213754597
Short name T190
Test name
Test status
Simulation time 345766052 ps
CPU time 3.67 seconds
Started May 14 01:09:55 PM PDT 24
Finished May 14 01:10:03 PM PDT 24
Peak memory 200620 kb
Host smart-5a8b4cd3-9c0b-447a-a7d5-b5d332282d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213754597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4213754597
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2748697374
Short name T305
Test name
Test status
Simulation time 440379212 ps
CPU time 6.84 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:07 PM PDT 24
Peak memory 200608 kb
Host smart-844132b4-69f4-4a9c-ae21-0a4d1b82ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748697374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2748697374
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1450960191
Short name T241
Test name
Test status
Simulation time 2132540146 ps
CPU time 575 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:19:36 PM PDT 24
Peak memory 735256 kb
Host smart-840b3fac-629e-48d4-8d94-824cb290e30a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450960191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1450960191
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2491543078
Short name T406
Test name
Test status
Simulation time 30995568 ps
CPU time 0.89 seconds
Started May 14 01:10:04 PM PDT 24
Finished May 14 01:10:10 PM PDT 24
Peak memory 199448 kb
Host smart-55af6499-b426-4198-bae1-fae9eef7e7b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491543078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2491543078
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3152831520
Short name T277
Test name
Test status
Simulation time 7608237621 ps
CPU time 42.97 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:43 PM PDT 24
Peak memory 200704 kb
Host smart-96be0c3a-6c00-4fd9-8f86-d7c39df2e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152831520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3152831520
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2896146403
Short name T216
Test name
Test status
Simulation time 2287557206 ps
CPU time 6.43 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:07 PM PDT 24
Peak memory 200736 kb
Host smart-e3b18244-e9df-4d8f-b3c1-2fd99783c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896146403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2896146403
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.871994065
Short name T372
Test name
Test status
Simulation time 98019055 ps
CPU time 1.03 seconds
Started May 14 01:09:52 PM PDT 24
Finished May 14 01:09:56 PM PDT 24
Peak memory 200152 kb
Host smart-c3d78ec4-980b-4bb7-9c56-0a68dce5fe2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871994065 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.871994065
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3220649323
Short name T352
Test name
Test status
Simulation time 143217909846 ps
CPU time 496.85 seconds
Started May 14 01:10:06 PM PDT 24
Finished May 14 01:18:28 PM PDT 24
Peak memory 200568 kb
Host smart-ffc1b20d-3f0c-477a-923c-ea7d37eea0f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220649323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3220649323
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2206504987
Short name T452
Test name
Test status
Simulation time 22604311 ps
CPU time 0.6 seconds
Started May 14 01:10:06 PM PDT 24
Finished May 14 01:10:11 PM PDT 24
Peak memory 195388 kb
Host smart-81f6f2bb-b084-4adf-91ee-50c1641ad29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206504987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2206504987
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3189032754
Short name T248
Test name
Test status
Simulation time 86187756 ps
CPU time 4.78 seconds
Started May 14 01:10:00 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 200564 kb
Host smart-4c7714f0-3654-49d3-8848-524a2f08aabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189032754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3189032754
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.855762059
Short name T349
Test name
Test status
Simulation time 7910092878 ps
CPU time 51.75 seconds
Started May 14 01:09:54 PM PDT 24
Finished May 14 01:10:50 PM PDT 24
Peak memory 200648 kb
Host smart-e9bf80b0-d820-46dc-83da-6b6491dd6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855762059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.855762059
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.320667708
Short name T292
Test name
Test status
Simulation time 27804854865 ps
CPU time 1040.8 seconds
Started May 14 01:10:15 PM PDT 24
Finished May 14 01:27:38 PM PDT 24
Peak memory 735260 kb
Host smart-248d0517-dc84-437b-8377-d48ea487efbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320667708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.320667708
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_smoke.688467572
Short name T411
Test name
Test status
Simulation time 261506115 ps
CPU time 4.25 seconds
Started May 14 01:09:58 PM PDT 24
Finished May 14 01:10:06 PM PDT 24
Peak memory 200876 kb
Host smart-489e9398-7fe6-4aee-b444-0895bcedabac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688467572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.688467572
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1640735346
Short name T134
Test name
Test status
Simulation time 72162277 ps
CPU time 1.39 seconds
Started May 14 01:10:06 PM PDT 24
Finished May 14 01:10:12 PM PDT 24
Peak memory 200644 kb
Host smart-ab32c8ea-27f6-4c49-8b59-4700dcca0a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640735346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1640735346
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1073358719
Short name T207
Test name
Test status
Simulation time 101641393383 ps
CPU time 471.49 seconds
Started May 14 01:09:59 PM PDT 24
Finished May 14 01:17:55 PM PDT 24
Peak memory 200640 kb
Host smart-f2b62dcd-3763-46e8-8db6-a5b4348134e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073358719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1073358719
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1614713712
Short name T421
Test name
Test status
Simulation time 24110267 ps
CPU time 0.58 seconds
Started May 14 01:10:19 PM PDT 24
Finished May 14 01:10:21 PM PDT 24
Peak memory 195996 kb
Host smart-f7633f6f-37d3-4c37-9e81-2da5fe2a4d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614713712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1614713712
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1371808854
Short name T314
Test name
Test status
Simulation time 278520630 ps
CPU time 8.16 seconds
Started May 14 01:10:13 PM PDT 24
Finished May 14 01:10:22 PM PDT 24
Peak memory 208872 kb
Host smart-4520fe31-bb9b-44fc-a3ac-7f4bf06075ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371808854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1371808854
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4096296140
Short name T276
Test name
Test status
Simulation time 931507826 ps
CPU time 25.11 seconds
Started May 14 01:09:54 PM PDT 24
Finished May 14 01:10:23 PM PDT 24
Peak memory 200572 kb
Host smart-3f224ca7-9775-434e-a633-bfae8d1e522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096296140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4096296140
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.790092659
Short name T214
Test name
Test status
Simulation time 661132858 ps
CPU time 145.48 seconds
Started May 14 01:10:15 PM PDT 24
Finished May 14 01:12:42 PM PDT 24
Peak memory 445284 kb
Host smart-2fafcc24-ce99-4cc0-a6d5-24e88e6f4f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790092659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.790092659
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1932933859
Short name T78
Test name
Test status
Simulation time 1173669763 ps
CPU time 74.38 seconds
Started May 14 01:10:13 PM PDT 24
Finished May 14 01:11:29 PM PDT 24
Peak memory 200680 kb
Host smart-992bc568-586e-4f60-8528-d898fe03308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932933859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1932933859
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2135785399
Short name T218
Test name
Test status
Simulation time 104372776 ps
CPU time 1.1 seconds
Started May 14 01:10:03 PM PDT 24
Finished May 14 01:10:10 PM PDT 24
Peak memory 200544 kb
Host smart-effc4c97-c5d0-49d9-afde-91d68e400c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135785399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2135785399
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1029854740
Short name T255
Test name
Test status
Simulation time 301696679 ps
CPU time 3.98 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:10 PM PDT 24
Peak memory 200608 kb
Host smart-10323432-6abc-4599-a65e-2af4f45f3d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029854740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1029854740
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.544172733
Short name T348
Test name
Test status
Simulation time 93774842 ps
CPU time 1.02 seconds
Started May 14 01:10:03 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 200168 kb
Host smart-788e50ac-b239-4768-b4ed-48acd7a235d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544172733 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.544172733
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3815686484
Short name T437
Test name
Test status
Simulation time 152440631629 ps
CPU time 419.34 seconds
Started May 14 01:09:58 PM PDT 24
Finished May 14 01:17:01 PM PDT 24
Peak memory 200644 kb
Host smart-6db7e6f5-8952-4d3d-a12d-727a5ea2582d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815686484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3815686484
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3440399842
Short name T471
Test name
Test status
Simulation time 1538501677 ps
CPU time 3.08 seconds
Started May 14 01:10:10 PM PDT 24
Finished May 14 01:10:15 PM PDT 24
Peak memory 200560 kb
Host smart-89fd160e-9970-412d-b0ae-ff4cd8df9d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440399842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3440399842
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3600570968
Short name T424
Test name
Test status
Simulation time 11099765 ps
CPU time 0.56 seconds
Started May 14 01:10:21 PM PDT 24
Finished May 14 01:10:23 PM PDT 24
Peak memory 196016 kb
Host smart-ff929f49-5222-45df-8cc3-b77476e52be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600570968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3600570968
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2609079778
Short name T126
Test name
Test status
Simulation time 438583211 ps
CPU time 23.4 seconds
Started May 14 01:10:04 PM PDT 24
Finished May 14 01:10:32 PM PDT 24
Peak memory 208868 kb
Host smart-f8dcb76a-ca74-457b-a82e-5e9aeb11ee86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609079778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2609079778
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4062146460
Short name T235
Test name
Test status
Simulation time 4838891804 ps
CPU time 65.07 seconds
Started May 14 01:10:15 PM PDT 24
Finished May 14 01:11:22 PM PDT 24
Peak memory 200604 kb
Host smart-128edb03-bb1f-4135-9255-c06f672bc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062146460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4062146460
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1544808456
Short name T425
Test name
Test status
Simulation time 3545125585 ps
CPU time 443.95 seconds
Started May 14 01:10:13 PM PDT 24
Finished May 14 01:17:38 PM PDT 24
Peak memory 677208 kb
Host smart-fa425157-254e-4d5a-9c14-ad98d2395e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544808456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1544808456
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2027078946
Short name T385
Test name
Test status
Simulation time 300494229 ps
CPU time 4.28 seconds
Started May 14 01:10:13 PM PDT 24
Finished May 14 01:10:18 PM PDT 24
Peak memory 200472 kb
Host smart-37b71bd2-943d-4a82-9ca2-ca455be11a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027078946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2027078946
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1762757068
Short name T272
Test name
Test status
Simulation time 332526829 ps
CPU time 5.53 seconds
Started May 14 01:10:10 PM PDT 24
Finished May 14 01:10:18 PM PDT 24
Peak memory 200596 kb
Host smart-445646ac-4a51-4c82-997a-f8e464835a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762757068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1762757068
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.88134835
Short name T378
Test name
Test status
Simulation time 115085149 ps
CPU time 1.28 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:07 PM PDT 24
Peak memory 200540 kb
Host smart-96f7008a-5df9-4b73-93b3-5bb89c000d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88134835 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.hmac_test_hmac_vectors.88134835
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2216408348
Short name T85
Test name
Test status
Simulation time 115436899244 ps
CPU time 513.6 seconds
Started May 14 01:10:00 PM PDT 24
Finished May 14 01:18:38 PM PDT 24
Peak memory 200652 kb
Host smart-c9f4dabf-29f2-44ee-b2de-ed8083605b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216408348 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2216408348
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.203219398
Short name T325
Test name
Test status
Simulation time 12784774 ps
CPU time 0.58 seconds
Started May 14 01:10:22 PM PDT 24
Finished May 14 01:10:24 PM PDT 24
Peak memory 195264 kb
Host smart-458f8791-6374-458e-9649-70e26fe5ee54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203219398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.203219398
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2058770761
Short name T290
Test name
Test status
Simulation time 1094631499 ps
CPU time 60.97 seconds
Started May 14 01:10:14 PM PDT 24
Finished May 14 01:11:16 PM PDT 24
Peak memory 234336 kb
Host smart-64cd3c7c-0632-4010-9c92-8b5fd329392d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058770761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2058770761
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1941701762
Short name T339
Test name
Test status
Simulation time 3531448885 ps
CPU time 17.15 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:23 PM PDT 24
Peak memory 200684 kb
Host smart-95645403-a05b-48b5-8ce1-2da9e258a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941701762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1941701762
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3355754182
Short name T258
Test name
Test status
Simulation time 383178427 ps
CPU time 81.77 seconds
Started May 14 01:10:09 PM PDT 24
Finished May 14 01:11:34 PM PDT 24
Peak memory 452588 kb
Host smart-5e6e0a7d-90fa-4f5d-a32a-9ae4e3564f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355754182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3355754182
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3642479149
Short name T358
Test name
Test status
Simulation time 1555906869 ps
CPU time 91.87 seconds
Started May 14 01:10:02 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200508 kb
Host smart-1633365e-0853-4e2c-9e2a-5e9f558ae212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642479149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3642479149
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.204304377
Short name T350
Test name
Test status
Simulation time 356409674 ps
CPU time 4.26 seconds
Started May 14 01:10:27 PM PDT 24
Finished May 14 01:10:33 PM PDT 24
Peak memory 200500 kb
Host smart-3ea760d9-9a14-447a-a9ef-3c3b1ce94646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204304377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.204304377
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1096507466
Short name T363
Test name
Test status
Simulation time 454071448 ps
CPU time 2.07 seconds
Started May 14 01:10:15 PM PDT 24
Finished May 14 01:10:19 PM PDT 24
Peak memory 200536 kb
Host smart-29e46059-09c1-408e-a385-21e963013c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096507466 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1096507466
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.36168096
Short name T25
Test name
Test status
Simulation time 110360552 ps
CPU time 1.22 seconds
Started May 14 01:10:20 PM PDT 24
Finished May 14 01:10:23 PM PDT 24
Peak memory 200540 kb
Host smart-4b0e0433-bc66-433d-ae13-fdc6db440e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168096 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_hmac_vectors.36168096
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3158160843
Short name T401
Test name
Test status
Simulation time 25724265292 ps
CPU time 476.08 seconds
Started May 14 01:10:05 PM PDT 24
Finished May 14 01:18:06 PM PDT 24
Peak memory 200564 kb
Host smart-1a4737c5-f057-4894-b7bc-c44922cfd4fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158160843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3158160843
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4285141389
Short name T43
Test name
Test status
Simulation time 15093092 ps
CPU time 0.59 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:20 PM PDT 24
Peak memory 195328 kb
Host smart-ef4acb87-efca-4c88-9f69-243e96e9ecb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285141389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4285141389
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.946089981
Short name T323
Test name
Test status
Simulation time 5071454104 ps
CPU time 52.43 seconds
Started May 14 01:09:13 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 233540 kb
Host smart-c11071c6-e2a9-4f84-b262-1473f627eec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946089981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.946089981
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3751895833
Short name T423
Test name
Test status
Simulation time 1500831317 ps
CPU time 31.79 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:52 PM PDT 24
Peak memory 200568 kb
Host smart-1d645487-baa7-439b-82e5-0f4aedf40594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751895833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3751895833
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2117749800
Short name T273
Test name
Test status
Simulation time 12942661179 ps
CPU time 942.04 seconds
Started May 14 01:09:16 PM PDT 24
Finished May 14 01:25:00 PM PDT 24
Peak memory 766092 kb
Host smart-5146b461-e3b3-414d-be23-9b6af0069391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117749800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2117749800
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3326122218
Short name T206
Test name
Test status
Simulation time 336197317 ps
CPU time 17.96 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:38 PM PDT 24
Peak memory 200568 kb
Host smart-b8862cb9-726e-468e-b48e-979268fd40c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326122218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3326122218
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2091972453
Short name T40
Test name
Test status
Simulation time 597733588 ps
CPU time 0.99 seconds
Started May 14 01:09:14 PM PDT 24
Finished May 14 01:09:17 PM PDT 24
Peak memory 219912 kb
Host smart-28dd56b0-a779-4374-9a0a-ba875d3a29de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091972453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2091972453
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3131929158
Short name T309
Test name
Test status
Simulation time 544824092 ps
CPU time 2.15 seconds
Started May 14 01:09:15 PM PDT 24
Finished May 14 01:09:19 PM PDT 24
Peak memory 200512 kb
Host smart-ddf852ec-904f-42e3-b7fb-8bd54b0b7a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131929158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3131929158
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2251924570
Short name T42
Test name
Test status
Simulation time 131860873 ps
CPU time 1.18 seconds
Started May 14 01:09:12 PM PDT 24
Finished May 14 01:09:15 PM PDT 24
Peak memory 200552 kb
Host smart-1c5774e3-c76c-4e2a-a2a2-7cff8f2e7ed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251924570 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2251924570
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2186233157
Short name T362
Test name
Test status
Simulation time 28754832782 ps
CPU time 507.85 seconds
Started May 14 01:09:11 PM PDT 24
Finished May 14 01:17:41 PM PDT 24
Peak memory 200636 kb
Host smart-e971017c-da48-41cc-b4dd-3b093da8aefa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186233157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2186233157
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.616483182
Short name T344
Test name
Test status
Simulation time 81141318 ps
CPU time 0.6 seconds
Started May 14 01:10:14 PM PDT 24
Finished May 14 01:10:15 PM PDT 24
Peak memory 196380 kb
Host smart-4d0e9e1e-e07a-4d63-aaab-bae32a076374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616483182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.616483182
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2398150196
Short name T446
Test name
Test status
Simulation time 5442840552 ps
CPU time 67.66 seconds
Started May 14 01:10:10 PM PDT 24
Finished May 14 01:11:20 PM PDT 24
Peak memory 233476 kb
Host smart-f94003c9-e9dd-4433-a8c9-587da4bda78e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398150196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2398150196
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3142815963
Short name T457
Test name
Test status
Simulation time 3318410706 ps
CPU time 25.56 seconds
Started May 14 01:10:27 PM PDT 24
Finished May 14 01:10:55 PM PDT 24
Peak memory 200668 kb
Host smart-e8323c7c-cc01-49c8-8a67-f58ca83fbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142815963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3142815963
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3794641841
Short name T146
Test name
Test status
Simulation time 9718667801 ps
CPU time 176.29 seconds
Started May 14 01:10:25 PM PDT 24
Finished May 14 01:13:23 PM PDT 24
Peak memory 655516 kb
Host smart-4617c0ff-a062-4d37-9b8b-8adcc6b56584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794641841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3794641841
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2744459011
Short name T165
Test name
Test status
Simulation time 29418690113 ps
CPU time 34.19 seconds
Started May 14 01:10:06 PM PDT 24
Finished May 14 01:10:45 PM PDT 24
Peak memory 200700 kb
Host smart-0211dc8d-f6f9-44fe-8548-44f7700cb3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744459011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2744459011
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.613659529
Short name T386
Test name
Test status
Simulation time 297352685 ps
CPU time 2.04 seconds
Started May 14 01:10:22 PM PDT 24
Finished May 14 01:10:25 PM PDT 24
Peak memory 200600 kb
Host smart-e75405be-617e-421d-b955-eb7c14e98c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613659529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.613659529
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1623198133
Short name T360
Test name
Test status
Simulation time 205163315 ps
CPU time 1.26 seconds
Started May 14 01:10:11 PM PDT 24
Finished May 14 01:10:14 PM PDT 24
Peak memory 200588 kb
Host smart-7fc218b0-bda9-49c7-bac1-bd42340aea27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623198133 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1623198133
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2319847564
Short name T416
Test name
Test status
Simulation time 27872658874 ps
CPU time 495.28 seconds
Started May 14 01:10:18 PM PDT 24
Finished May 14 01:18:34 PM PDT 24
Peak memory 200684 kb
Host smart-9b608548-a095-4ac0-8c89-7f707364a197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319847564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2319847564
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3143785830
Short name T250
Test name
Test status
Simulation time 11723949 ps
CPU time 0.63 seconds
Started May 14 01:10:22 PM PDT 24
Finished May 14 01:10:24 PM PDT 24
Peak memory 196004 kb
Host smart-dc9ccd7e-945c-4be7-a8d7-8f39c90e7661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143785830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3143785830
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2390820699
Short name T422
Test name
Test status
Simulation time 2822901920 ps
CPU time 38.25 seconds
Started May 14 01:10:23 PM PDT 24
Finished May 14 01:11:03 PM PDT 24
Peak memory 217024 kb
Host smart-a2c34a0f-88e7-49c9-abfc-4985ac39d2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390820699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2390820699
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4067022023
Short name T414
Test name
Test status
Simulation time 4101010078 ps
CPU time 18.86 seconds
Started May 14 01:10:21 PM PDT 24
Finished May 14 01:10:42 PM PDT 24
Peak memory 200696 kb
Host smart-247e5cea-d4ff-4581-a12e-c7fda87f437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067022023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4067022023
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1022894730
Short name T113
Test name
Test status
Simulation time 3172557372 ps
CPU time 833.39 seconds
Started May 14 01:10:22 PM PDT 24
Finished May 14 01:24:17 PM PDT 24
Peak memory 702624 kb
Host smart-7da6b41a-f9a8-4006-aeff-60b309714bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022894730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1022894730
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2111200190
Short name T244
Test name
Test status
Simulation time 6145748059 ps
CPU time 117.25 seconds
Started May 14 01:10:09 PM PDT 24
Finished May 14 01:12:09 PM PDT 24
Peak memory 200780 kb
Host smart-f0c82ac1-474d-4bac-93ac-29c295204e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111200190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2111200190
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2186362066
Short name T221
Test name
Test status
Simulation time 75534918 ps
CPU time 2.34 seconds
Started May 14 01:10:29 PM PDT 24
Finished May 14 01:10:33 PM PDT 24
Peak memory 200576 kb
Host smart-f997d60e-301c-4b8f-a2d9-b18103372c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186362066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2186362066
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3007059987
Short name T33
Test name
Test status
Simulation time 42754159893 ps
CPU time 650.54 seconds
Started May 14 01:10:25 PM PDT 24
Finished May 14 01:21:18 PM PDT 24
Peak memory 233156 kb
Host smart-eb5a1d3e-94fa-4bba-9c11-979f088dafe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007059987 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3007059987
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3214520127
Short name T192
Test name
Test status
Simulation time 167200801 ps
CPU time 1.06 seconds
Started May 14 01:10:15 PM PDT 24
Finished May 14 01:10:18 PM PDT 24
Peak memory 200004 kb
Host smart-55d79ea4-dc15-4934-94d7-952cbf76cb40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214520127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3214520127
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3408433710
Short name T254
Test name
Test status
Simulation time 30516766437 ps
CPU time 415.82 seconds
Started May 14 01:10:19 PM PDT 24
Finished May 14 01:17:16 PM PDT 24
Peak memory 200664 kb
Host smart-7b504453-fd2b-4efd-99e5-cc866681035d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408433710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3408433710
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3257459794
Short name T426
Test name
Test status
Simulation time 13063098 ps
CPU time 0.6 seconds
Started May 14 01:10:35 PM PDT 24
Finished May 14 01:10:37 PM PDT 24
Peak memory 195360 kb
Host smart-b59f63e3-9ddf-45cb-86b3-365727063f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257459794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3257459794
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.485874982
Short name T334
Test name
Test status
Simulation time 753322236 ps
CPU time 10.19 seconds
Started May 14 01:10:26 PM PDT 24
Finished May 14 01:10:38 PM PDT 24
Peak memory 216740 kb
Host smart-3d5f3872-6aed-4817-98ce-d0a4632ec5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485874982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.485874982
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4203573296
Short name T384
Test name
Test status
Simulation time 507653361 ps
CPU time 26.89 seconds
Started May 14 01:10:26 PM PDT 24
Finished May 14 01:10:55 PM PDT 24
Peak memory 200604 kb
Host smart-0adb4b4e-192a-4b25-ba9a-40c9441fca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203573296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4203573296
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1824824949
Short name T70
Test name
Test status
Simulation time 2022380729 ps
CPU time 28.98 seconds
Started May 14 01:10:23 PM PDT 24
Finished May 14 01:10:54 PM PDT 24
Peak memory 200664 kb
Host smart-1335e3fd-3056-486d-8190-1d651604a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824824949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1824824949
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4095749165
Short name T458
Test name
Test status
Simulation time 541834086 ps
CPU time 2.54 seconds
Started May 14 01:10:26 PM PDT 24
Finished May 14 01:10:30 PM PDT 24
Peak memory 200600 kb
Host smart-6c3deff1-6526-4c6c-b4af-6197dcc7f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095749165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4095749165
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.437364046
Short name T318
Test name
Test status
Simulation time 224573638 ps
CPU time 1.24 seconds
Started May 14 01:10:24 PM PDT 24
Finished May 14 01:10:27 PM PDT 24
Peak memory 200528 kb
Host smart-3721f59e-559c-41d2-b433-e933b3e65e84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437364046 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.437364046
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3119020009
Short name T370
Test name
Test status
Simulation time 34060879 ps
CPU time 0.58 seconds
Started May 14 01:10:18 PM PDT 24
Finished May 14 01:10:19 PM PDT 24
Peak memory 196184 kb
Host smart-4e8c3193-8b1c-4bfd-a32d-6d277fdf7f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119020009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3119020009
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.917301293
Short name T409
Test name
Test status
Simulation time 3984433905 ps
CPU time 37.24 seconds
Started May 14 01:10:22 PM PDT 24
Finished May 14 01:11:00 PM PDT 24
Peak memory 221184 kb
Host smart-0bc127b6-34bd-4478-9e1b-17e5da1edffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917301293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.917301293
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.872398031
Short name T472
Test name
Test status
Simulation time 2266710671 ps
CPU time 5.14 seconds
Started May 14 01:10:24 PM PDT 24
Finished May 14 01:10:31 PM PDT 24
Peak memory 200664 kb
Host smart-267d5272-cd69-4db5-b45f-8f2159d06703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872398031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.872398031
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2497041283
Short name T412
Test name
Test status
Simulation time 6733133465 ps
CPU time 417.85 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:17:32 PM PDT 24
Peak memory 622768 kb
Host smart-c567b169-df0f-4aec-bd63-82fc2cd3c65e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497041283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2497041283
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1912287038
Short name T2
Test name
Test status
Simulation time 885187295 ps
CPU time 45.26 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:11:19 PM PDT 24
Peak memory 200656 kb
Host smart-bc0869cf-0019-4209-ad57-d43fa43852e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912287038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1912287038
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3307127160
Short name T337
Test name
Test status
Simulation time 10505587317 ps
CPU time 10.73 seconds
Started May 14 01:10:25 PM PDT 24
Finished May 14 01:10:37 PM PDT 24
Peak memory 200748 kb
Host smart-dd79e8c1-cb3c-4096-a5ab-b87f31ceaffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307127160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3307127160
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1240345160
Short name T12
Test name
Test status
Simulation time 873333735 ps
CPU time 6.73 seconds
Started May 14 01:10:24 PM PDT 24
Finished May 14 01:10:33 PM PDT 24
Peak memory 200576 kb
Host smart-931c7320-20b3-4275-bd55-ae86164a134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240345160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1240345160
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.4160606240
Short name T51
Test name
Test status
Simulation time 113227212 ps
CPU time 1.23 seconds
Started May 14 01:10:26 PM PDT 24
Finished May 14 01:10:29 PM PDT 24
Peak memory 200500 kb
Host smart-bb1fa8e1-ea28-4239-88a7-55da50f4b9e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160606240 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.4160606240
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1955953771
Short name T287
Test name
Test status
Simulation time 14922261886 ps
CPU time 427.1 seconds
Started May 14 01:10:27 PM PDT 24
Finished May 14 01:17:36 PM PDT 24
Peak memory 200632 kb
Host smart-4ca80a00-aa05-4caf-a521-b98344bc6fb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955953771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1955953771
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.762570814
Short name T80
Test name
Test status
Simulation time 19696472 ps
CPU time 0.61 seconds
Started May 14 01:10:38 PM PDT 24
Finished May 14 01:10:40 PM PDT 24
Peak memory 195984 kb
Host smart-0dc5ab7a-452b-4554-875b-9cca0123a7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762570814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.762570814
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1034656782
Short name T262
Test name
Test status
Simulation time 2306152127 ps
CPU time 28.23 seconds
Started May 14 01:10:34 PM PDT 24
Finished May 14 01:11:04 PM PDT 24
Peak memory 200712 kb
Host smart-dafea2d2-c3f2-466a-8918-76c37bf26a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034656782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1034656782
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1133258230
Short name T264
Test name
Test status
Simulation time 784499221 ps
CPU time 3.47 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:10:38 PM PDT 24
Peak memory 200584 kb
Host smart-820376df-e329-4723-9e3e-e4d3c4854414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133258230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1133258230
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1299019535
Short name T220
Test name
Test status
Simulation time 4919159915 ps
CPU time 649.55 seconds
Started May 14 01:10:27 PM PDT 24
Finished May 14 01:21:18 PM PDT 24
Peak memory 693768 kb
Host smart-ff7e227c-9e66-4d1b-8ec4-dd83225fad3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299019535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1299019535
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4137233324
Short name T16
Test name
Test status
Simulation time 1732200931 ps
CPU time 24.25 seconds
Started May 14 01:10:27 PM PDT 24
Finished May 14 01:10:53 PM PDT 24
Peak memory 200636 kb
Host smart-aefef20d-b2e6-410f-be0f-4dadf8facd00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137233324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4137233324
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1468076912
Short name T111
Test name
Test status
Simulation time 4890042208 ps
CPU time 64.74 seconds
Started May 14 01:10:28 PM PDT 24
Finished May 14 01:11:35 PM PDT 24
Peak memory 200668 kb
Host smart-f2863aa3-88d0-4534-adde-025422f138cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468076912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1468076912
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2869931452
Short name T114
Test name
Test status
Simulation time 204057684 ps
CPU time 3.19 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:10:38 PM PDT 24
Peak memory 200548 kb
Host smart-cb4ed163-8aa8-4926-b8ba-3c74a161d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869931452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2869931452
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.63014500
Short name T427
Test name
Test status
Simulation time 246905443 ps
CPU time 1.33 seconds
Started May 14 01:10:28 PM PDT 24
Finished May 14 01:10:31 PM PDT 24
Peak memory 200492 kb
Host smart-9fbf55c8-ba58-4514-9a7b-fc6000f9c8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63014500 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.hmac_test_hmac_vectors.63014500
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.575748974
Short name T195
Test name
Test status
Simulation time 13876033318 ps
CPU time 400.02 seconds
Started May 14 01:10:30 PM PDT 24
Finished May 14 01:17:12 PM PDT 24
Peak memory 200616 kb
Host smart-4eec1a41-8036-4159-b920-9436eac59a20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575748974 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.575748974
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3669198443
Short name T140
Test name
Test status
Simulation time 12061280 ps
CPU time 0.6 seconds
Started May 14 01:10:40 PM PDT 24
Finished May 14 01:10:43 PM PDT 24
Peak memory 197108 kb
Host smart-e9fe9822-f6ae-40bb-8dc5-0f7304df7d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669198443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3669198443
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3360583442
Short name T257
Test name
Test status
Simulation time 1103033220 ps
CPU time 61.48 seconds
Started May 14 01:10:31 PM PDT 24
Finished May 14 01:11:34 PM PDT 24
Peak memory 225172 kb
Host smart-b81b9b4a-31b8-4e4a-9eec-025028fb2ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360583442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3360583442
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2077389933
Short name T328
Test name
Test status
Simulation time 2212170723 ps
CPU time 31.06 seconds
Started May 14 01:10:39 PM PDT 24
Finished May 14 01:11:12 PM PDT 24
Peak memory 200948 kb
Host smart-a7dda519-6f2c-4fa1-87e0-e3b16aa4230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077389933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2077389933
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.931688595
Short name T22
Test name
Test status
Simulation time 579499270 ps
CPU time 156.8 seconds
Started May 14 01:10:30 PM PDT 24
Finished May 14 01:13:09 PM PDT 24
Peak memory 610876 kb
Host smart-627ffd82-2c2f-4ef9-8600-4613521b8606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931688595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.931688595
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2620144823
Short name T136
Test name
Test status
Simulation time 27209954784 ps
CPU time 94.07 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:12:08 PM PDT 24
Peak memory 200660 kb
Host smart-9f655071-7511-432f-9dd5-4c3274b87a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620144823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2620144823
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.225010309
Short name T469
Test name
Test status
Simulation time 393675540 ps
CPU time 3.35 seconds
Started May 14 01:10:29 PM PDT 24
Finished May 14 01:10:34 PM PDT 24
Peak memory 200576 kb
Host smart-6d5cc2d7-2a6d-426b-9199-5f46a4590470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225010309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.225010309
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3067544512
Short name T152
Test name
Test status
Simulation time 749233369 ps
CPU time 1.41 seconds
Started May 14 01:10:29 PM PDT 24
Finished May 14 01:10:33 PM PDT 24
Peak memory 200488 kb
Host smart-8441e752-3251-4a11-a557-159815112504
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067544512 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3067544512
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3306035050
Short name T145
Test name
Test status
Simulation time 28069942905 ps
CPU time 500.62 seconds
Started May 14 01:10:33 PM PDT 24
Finished May 14 01:18:55 PM PDT 24
Peak memory 200628 kb
Host smart-7e9670d6-c56c-4d23-912f-ca2d2ea67ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306035050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3306035050
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.698718313
Short name T297
Test name
Test status
Simulation time 39463729 ps
CPU time 0.57 seconds
Started May 14 01:10:43 PM PDT 24
Finished May 14 01:10:47 PM PDT 24
Peak memory 195328 kb
Host smart-858c1d7a-3eec-46f1-95fb-48ec7a0524f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698718313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.698718313
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1889214354
Short name T438
Test name
Test status
Simulation time 2788373552 ps
CPU time 35.5 seconds
Started May 14 01:10:35 PM PDT 24
Finished May 14 01:11:12 PM PDT 24
Peak memory 248672 kb
Host smart-0c2c4915-9818-4dc0-97eb-0b648d294062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889214354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1889214354
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3925753511
Short name T307
Test name
Test status
Simulation time 2152286529 ps
CPU time 590.35 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:20:48 PM PDT 24
Peak memory 732040 kb
Host smart-bde8aa74-8c4d-488a-b82b-36339754e3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925753511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3925753511
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4004309341
Short name T10
Test name
Test status
Simulation time 6810048020 ps
CPU time 39.16 seconds
Started May 14 01:10:41 PM PDT 24
Finished May 14 01:11:24 PM PDT 24
Peak memory 200676 kb
Host smart-d6cc4db0-4a18-4243-8a58-1e6f5088a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004309341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4004309341
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3222641524
Short name T288
Test name
Test status
Simulation time 548193310 ps
CPU time 5.87 seconds
Started May 14 01:10:41 PM PDT 24
Finished May 14 01:10:50 PM PDT 24
Peak memory 200528 kb
Host smart-2fadaee4-a1fc-4a1d-ab3b-142c8b6af5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222641524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3222641524
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1531830397
Short name T432
Test name
Test status
Simulation time 54829385 ps
CPU time 1.23 seconds
Started May 14 01:10:39 PM PDT 24
Finished May 14 01:10:43 PM PDT 24
Peak memory 200532 kb
Host smart-348e0adf-7a54-4137-ad0c-a46405695ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531830397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1531830397
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.560032914
Short name T187
Test name
Test status
Simulation time 76154516220 ps
CPU time 381.93 seconds
Started May 14 01:10:56 PM PDT 24
Finished May 14 01:17:21 PM PDT 24
Peak memory 200756 kb
Host smart-8261dc56-d2e4-45bc-90ef-b35e82ddf870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560032914 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.560032914
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4211029978
Short name T150
Test name
Test status
Simulation time 85602361 ps
CPU time 0.57 seconds
Started May 14 01:10:40 PM PDT 24
Finished May 14 01:10:42 PM PDT 24
Peak memory 195360 kb
Host smart-c75c2665-cef6-45b0-8c65-9edc5d7d4a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211029978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4211029978
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1242222191
Short name T367
Test name
Test status
Simulation time 2073084699 ps
CPU time 19.29 seconds
Started May 14 01:10:40 PM PDT 24
Finished May 14 01:11:02 PM PDT 24
Peak memory 200664 kb
Host smart-4cfbfe02-6333-4dc5-99b3-f90c645cf4e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242222191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1242222191
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4051004757
Short name T219
Test name
Test status
Simulation time 480568805 ps
CPU time 5.83 seconds
Started May 14 01:10:42 PM PDT 24
Finished May 14 01:10:51 PM PDT 24
Peak memory 200476 kb
Host smart-02cb8623-0eeb-4d5d-a6f9-93c64920dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051004757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4051004757
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.524555183
Short name T302
Test name
Test status
Simulation time 44684612797 ps
CPU time 1086.22 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:29:04 PM PDT 24
Peak memory 707620 kb
Host smart-40e0af9c-a818-4a56-9905-42ef3e22aca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524555183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.524555183
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1874612070
Short name T353
Test name
Test status
Simulation time 3199231506 ps
CPU time 11.84 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:11:10 PM PDT 24
Peak memory 200748 kb
Host smart-5d249731-91a1-41c1-8546-6113ade88c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874612070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1874612070
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4049967477
Short name T174
Test name
Test status
Simulation time 292238769 ps
CPU time 2.12 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:11:00 PM PDT 24
Peak memory 200648 kb
Host smart-b39d4e59-d60a-46a2-9846-4aec4d026787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049967477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4049967477
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1659430902
Short name T229
Test name
Test status
Simulation time 52014056 ps
CPU time 1.28 seconds
Started May 14 01:10:37 PM PDT 24
Finished May 14 01:10:40 PM PDT 24
Peak memory 200664 kb
Host smart-40d14a7a-1cf0-4d03-925f-c6fe361da111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659430902 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1659430902
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1023780982
Short name T474
Test name
Test status
Simulation time 26192340666 ps
CPU time 352.75 seconds
Started May 14 01:10:40 PM PDT 24
Finished May 14 01:16:35 PM PDT 24
Peak memory 200652 kb
Host smart-4061cb44-767d-480f-a093-e6b60d9f372a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023780982 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1023780982
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4179725311
Short name T234
Test name
Test status
Simulation time 46254259 ps
CPU time 0.58 seconds
Started May 14 01:10:50 PM PDT 24
Finished May 14 01:10:54 PM PDT 24
Peak memory 196024 kb
Host smart-f004204e-222f-471f-a342-99c3e66f0bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179725311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4179725311
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1523568611
Short name T269
Test name
Test status
Simulation time 709480440 ps
CPU time 37.53 seconds
Started May 14 01:10:38 PM PDT 24
Finished May 14 01:11:18 PM PDT 24
Peak memory 230360 kb
Host smart-f5d0bf4b-45e1-46f6-9c20-78557424ae97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523568611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1523568611
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.941622043
Short name T63
Test name
Test status
Simulation time 1229986136 ps
CPU time 62.74 seconds
Started May 14 01:10:45 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 200640 kb
Host smart-003883ca-8a3f-4e3d-aa7c-556ca54d1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941622043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.941622043
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2299918174
Short name T163
Test name
Test status
Simulation time 9705573046 ps
CPU time 725.73 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:22:56 PM PDT 24
Peak memory 708108 kb
Host smart-e5d8c939-b12f-4ea9-bc0f-f91e33256f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299918174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2299918174
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1280750390
Short name T441
Test name
Test status
Simulation time 384472601 ps
CPU time 5.91 seconds
Started May 14 01:10:52 PM PDT 24
Finished May 14 01:11:00 PM PDT 24
Peak memory 200404 kb
Host smart-b0af8ae0-ca06-4eee-a81d-86f10e1b399f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280750390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1280750390
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2299507318
Short name T278
Test name
Test status
Simulation time 837543952 ps
CPU time 11.89 seconds
Started May 14 01:10:39 PM PDT 24
Finished May 14 01:10:53 PM PDT 24
Peak memory 200560 kb
Host smart-19f55e33-3345-46c6-8ff0-faa4a2b21ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299507318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2299507318
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.993119115
Short name T154
Test name
Test status
Simulation time 107769352 ps
CPU time 1.24 seconds
Started May 14 01:10:44 PM PDT 24
Finished May 14 01:10:49 PM PDT 24
Peak memory 200588 kb
Host smart-bf662ee3-2986-47b2-a1cf-e87548cdb03f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993119115 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.993119115
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1578988275
Short name T298
Test name
Test status
Simulation time 27989347725 ps
CPU time 457.94 seconds
Started May 14 01:10:56 PM PDT 24
Finished May 14 01:18:37 PM PDT 24
Peak memory 200708 kb
Host smart-e4635e0d-1d90-4107-9227-ef28c53894a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578988275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1578988275
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.436824804
Short name T381
Test name
Test status
Simulation time 20379568 ps
CPU time 0.6 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:10:50 PM PDT 24
Peak memory 197056 kb
Host smart-230901a4-abdb-4a41-881e-b0ad06d14f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436824804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.436824804
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.4160426139
Short name T181
Test name
Test status
Simulation time 1193160585 ps
CPU time 18.49 seconds
Started May 14 01:11:00 PM PDT 24
Finished May 14 01:11:21 PM PDT 24
Peak memory 228268 kb
Host smart-81f090c3-6fb1-458a-91b8-b8bff1de5585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160426139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4160426139
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2531630395
Short name T171
Test name
Test status
Simulation time 46974332936 ps
CPU time 44.71 seconds
Started May 14 01:10:45 PM PDT 24
Finished May 14 01:11:33 PM PDT 24
Peak memory 200796 kb
Host smart-e1818a51-6024-4ab5-a586-cc0673d6a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531630395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2531630395
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4058360648
Short name T9
Test name
Test status
Simulation time 1024456221 ps
CPU time 235.4 seconds
Started May 14 01:10:45 PM PDT 24
Finished May 14 01:14:44 PM PDT 24
Peak memory 628424 kb
Host smart-084c3572-1bc9-41fd-9324-c80560a6dee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058360648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4058360648
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3401475363
Short name T402
Test name
Test status
Simulation time 7657908509 ps
CPU time 27.5 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:11:18 PM PDT 24
Peak memory 200824 kb
Host smart-7d2615c4-c678-4f7e-a638-f6a460aa3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401475363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3401475363
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2818759731
Short name T212
Test name
Test status
Simulation time 428282398 ps
CPU time 6.2 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:10:56 PM PDT 24
Peak memory 200632 kb
Host smart-c009e6c3-b2b0-42d3-b6d6-d3e32ea9b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818759731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2818759731
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.252064818
Short name T303
Test name
Test status
Simulation time 363337085 ps
CPU time 1.12 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:10:52 PM PDT 24
Peak memory 200032 kb
Host smart-b1a1c4ef-499c-4646-8f1f-87574163197c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252064818 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.252064818
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.729640885
Short name T153
Test name
Test status
Simulation time 83477850405 ps
CPU time 529.64 seconds
Started May 14 01:10:49 PM PDT 24
Finished May 14 01:19:42 PM PDT 24
Peak memory 200672 kb
Host smart-6bc9f60c-9194-4e4d-951a-7fc0ed864cda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729640885 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.729640885
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.30329340
Short name T460
Test name
Test status
Simulation time 11809180 ps
CPU time 0.58 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:21 PM PDT 24
Peak memory 196372 kb
Host smart-e708175b-c841-4fc2-8fe6-8151a0799b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.30329340
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1730221821
Short name T18
Test name
Test status
Simulation time 4402070734 ps
CPU time 63.15 seconds
Started May 14 01:09:19 PM PDT 24
Finished May 14 01:10:24 PM PDT 24
Peak memory 230444 kb
Host smart-1bbbc675-03a9-4a27-be25-2cb59a8e0430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730221821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1730221821
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1241378897
Short name T107
Test name
Test status
Simulation time 14306645237 ps
CPU time 1088.15 seconds
Started May 14 01:09:10 PM PDT 24
Finished May 14 01:27:21 PM PDT 24
Peak memory 733924 kb
Host smart-5d03c5be-8b98-4b79-8ed7-7e6ff52a4d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241378897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1241378897
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.935619940
Short name T285
Test name
Test status
Simulation time 10433903266 ps
CPU time 48.61 seconds
Started May 14 01:09:16 PM PDT 24
Finished May 14 01:10:06 PM PDT 24
Peak memory 200716 kb
Host smart-9dd1a4d9-0fcf-4363-b881-20358087a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935619940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.935619940
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.306652827
Short name T26
Test name
Test status
Simulation time 121729958 ps
CPU time 0.95 seconds
Started May 14 01:09:15 PM PDT 24
Finished May 14 01:09:18 PM PDT 24
Peak memory 218900 kb
Host smart-f4129ea5-782e-4c24-967c-ccacf343d11b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306652827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.306652827
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.411385842
Short name T157
Test name
Test status
Simulation time 583386109 ps
CPU time 6.43 seconds
Started May 14 01:09:17 PM PDT 24
Finished May 14 01:09:25 PM PDT 24
Peak memory 200644 kb
Host smart-29ab88e3-9a89-4701-a5f2-d773ebd669ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411385842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.411385842
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1024176201
Short name T138
Test name
Test status
Simulation time 193729231 ps
CPU time 1.37 seconds
Started May 14 01:09:17 PM PDT 24
Finished May 14 01:09:21 PM PDT 24
Peak memory 200576 kb
Host smart-5cf21097-6f7e-4ee7-9798-ab840a996c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024176201 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1024176201
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3478112299
Short name T240
Test name
Test status
Simulation time 30355233859 ps
CPU time 406.01 seconds
Started May 14 01:09:17 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 200672 kb
Host smart-d334cb6d-9683-43c4-9068-73ff82a7e9f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478112299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3478112299
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4031930119
Short name T19
Test name
Test status
Simulation time 15075456 ps
CPU time 0.6 seconds
Started May 14 01:10:50 PM PDT 24
Finished May 14 01:10:54 PM PDT 24
Peak memory 196384 kb
Host smart-39521626-8663-4b8d-b11e-308634418679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031930119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4031930119
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3732649783
Short name T243
Test name
Test status
Simulation time 512290893 ps
CPU time 6.26 seconds
Started May 14 01:10:50 PM PDT 24
Finished May 14 01:10:59 PM PDT 24
Peak memory 208808 kb
Host smart-12c87599-d338-4d73-8011-7e56a6366288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732649783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3732649783
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2095608445
Short name T347
Test name
Test status
Simulation time 624321291 ps
CPU time 5.17 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:10:55 PM PDT 24
Peak memory 200576 kb
Host smart-b646a614-1d0f-4946-b63d-338706ae5ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095608445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2095608445
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.415784917
Short name T357
Test name
Test status
Simulation time 525108288 ps
CPU time 100.45 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:12:40 PM PDT 24
Peak memory 436656 kb
Host smart-6f0d3678-e874-4012-83f2-857d0c2990d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415784917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.415784917
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2604240773
Short name T132
Test name
Test status
Simulation time 30780921165 ps
CPU time 100.69 seconds
Started May 14 01:10:46 PM PDT 24
Finished May 14 01:12:29 PM PDT 24
Peak memory 200728 kb
Host smart-a839218a-97ae-49d4-abe4-2382dea694e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604240773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2604240773
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3826141013
Short name T180
Test name
Test status
Simulation time 47496586 ps
CPU time 1.79 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:11:02 PM PDT 24
Peak memory 200612 kb
Host smart-5be7fa22-99d2-48da-819c-3d63b4a309db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826141013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3826141013
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2774010225
Short name T342
Test name
Test status
Simulation time 60412231 ps
CPU time 1.29 seconds
Started May 14 01:10:54 PM PDT 24
Finished May 14 01:10:58 PM PDT 24
Peak memory 200612 kb
Host smart-0342b739-9580-4fd6-b0d1-f94ad9febbe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774010225 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2774010225
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2000253047
Short name T17
Test name
Test status
Simulation time 22285611898 ps
CPU time 439.29 seconds
Started May 14 01:10:49 PM PDT 24
Finished May 14 01:18:11 PM PDT 24
Peak memory 200684 kb
Host smart-f391cf1f-fc4a-4e1b-9d8c-9a2d2b3990b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000253047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2000253047
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1315819525
Short name T338
Test name
Test status
Simulation time 20478005 ps
CPU time 0.57 seconds
Started May 14 01:11:00 PM PDT 24
Finished May 14 01:11:03 PM PDT 24
Peak memory 196096 kb
Host smart-80e8c52b-2f68-4cb2-8fd5-a020f6dea619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315819525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1315819525
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1249717892
Short name T291
Test name
Test status
Simulation time 558208845 ps
CPU time 28.94 seconds
Started May 14 01:10:53 PM PDT 24
Finished May 14 01:11:25 PM PDT 24
Peak memory 200644 kb
Host smart-3328a469-7a74-4f91-9a47-f157b4fdf70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249717892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1249717892
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.908591292
Short name T108
Test name
Test status
Simulation time 6432140138 ps
CPU time 20.93 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:11:22 PM PDT 24
Peak memory 200684 kb
Host smart-1861d82a-2e98-4a09-a15c-de1a983c685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908591292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.908591292
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2390130931
Short name T188
Test name
Test status
Simulation time 3208754804 ps
CPU time 342.23 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:16:41 PM PDT 24
Peak memory 640696 kb
Host smart-57ae81b9-4726-40fa-8693-a56e350e4b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390130931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2390130931
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2833243145
Short name T14
Test name
Test status
Simulation time 119105427 ps
CPU time 6.47 seconds
Started May 14 01:11:03 PM PDT 24
Finished May 14 01:11:13 PM PDT 24
Peak memory 200492 kb
Host smart-ff718e28-3cde-44f5-beff-99392a80d2a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833243145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2833243145
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.382450503
Short name T398
Test name
Test status
Simulation time 1022370797 ps
CPU time 62.09 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:12:02 PM PDT 24
Peak memory 200584 kb
Host smart-0b9949ca-bdb1-40f2-a28c-e7fa152e1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382450503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.382450503
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3474084309
Short name T268
Test name
Test status
Simulation time 899574632 ps
CPU time 7.12 seconds
Started May 14 01:10:47 PM PDT 24
Finished May 14 01:10:57 PM PDT 24
Peak memory 200596 kb
Host smart-838ca6cc-3351-4183-9d30-a7af04c82e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474084309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3474084309
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1766742389
Short name T209
Test name
Test status
Simulation time 76078506 ps
CPU time 0.95 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:11:02 PM PDT 24
Peak memory 199208 kb
Host smart-ecc75303-92b4-4798-b7cc-0470d6e375bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766742389 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1766742389
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2151116239
Short name T295
Test name
Test status
Simulation time 102122227328 ps
CPU time 486.19 seconds
Started May 14 01:10:54 PM PDT 24
Finished May 14 01:19:03 PM PDT 24
Peak memory 200632 kb
Host smart-b381334f-db96-43c8-ae71-f99906fd64b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151116239 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2151116239
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3892650569
Short name T271
Test name
Test status
Simulation time 14334349 ps
CPU time 0.58 seconds
Started May 14 01:10:59 PM PDT 24
Finished May 14 01:11:02 PM PDT 24
Peak memory 196368 kb
Host smart-b37f2d1e-9d92-43d9-9e67-31b527c212f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892650569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3892650569
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1127141789
Short name T125
Test name
Test status
Simulation time 661194274 ps
CPU time 34.97 seconds
Started May 14 01:10:59 PM PDT 24
Finished May 14 01:11:37 PM PDT 24
Peak memory 216260 kb
Host smart-3f670dec-da2a-4639-a8c6-fbde79357187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127141789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1127141789
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1438227594
Short name T436
Test name
Test status
Simulation time 1833313930 ps
CPU time 25.29 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:11:25 PM PDT 24
Peak memory 200624 kb
Host smart-ecaef38e-7922-43f1-b57d-39e480bf6b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438227594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1438227594
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3953212194
Short name T332
Test name
Test status
Simulation time 2381703905 ps
CPU time 325.16 seconds
Started May 14 01:10:56 PM PDT 24
Finished May 14 01:16:24 PM PDT 24
Peak memory 690304 kb
Host smart-16222b3c-3f57-4dd6-93c9-3e423ade94ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953212194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3953212194
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.752894359
Short name T144
Test name
Test status
Simulation time 9272539441 ps
CPU time 29.97 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:11:28 PM PDT 24
Peak memory 200628 kb
Host smart-ae19018f-318d-419b-aa68-f59969281413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752894359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.752894359
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2886708932
Short name T329
Test name
Test status
Simulation time 52934040 ps
CPU time 1.09 seconds
Started May 14 01:10:55 PM PDT 24
Finished May 14 01:10:59 PM PDT 24
Peak memory 200408 kb
Host smart-82eab109-79b1-4831-b5fb-b96a5168c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886708932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2886708932
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3863269894
Short name T161
Test name
Test status
Simulation time 40424625279 ps
CPU time 561.91 seconds
Started May 14 01:11:01 PM PDT 24
Finished May 14 01:20:27 PM PDT 24
Peak memory 200752 kb
Host smart-7cd43db5-48e7-4d99-917f-cc72fdcef138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863269894 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3863269894
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2218938980
Short name T365
Test name
Test status
Simulation time 80679744 ps
CPU time 1.29 seconds
Started May 14 01:11:00 PM PDT 24
Finished May 14 01:11:04 PM PDT 24
Peak memory 200536 kb
Host smart-c50bb99d-19d4-45ff-81f3-146044f7ff01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218938980 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2218938980
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.732538636
Short name T420
Test name
Test status
Simulation time 101139245583 ps
CPU time 435.63 seconds
Started May 14 01:10:54 PM PDT 24
Finished May 14 01:18:12 PM PDT 24
Peak memory 200524 kb
Host smart-78be4c65-bb2f-441d-a293-f00210f11740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732538636 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.732538636
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2754501956
Short name T166
Test name
Test status
Simulation time 13589094 ps
CPU time 0.65 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:11:01 PM PDT 24
Peak memory 196316 kb
Host smart-88b75774-0b7f-4172-a4fb-d37d3de72a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754501956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2754501956
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.903782035
Short name T265
Test name
Test status
Simulation time 138300648 ps
CPU time 6.35 seconds
Started May 14 01:10:53 PM PDT 24
Finished May 14 01:11:02 PM PDT 24
Peak memory 200536 kb
Host smart-82d33c24-238b-40d3-bffe-c0e3a82441f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903782035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.903782035
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4018392816
Short name T431
Test name
Test status
Simulation time 618824534 ps
CPU time 6.48 seconds
Started May 14 01:11:02 PM PDT 24
Finished May 14 01:11:13 PM PDT 24
Peak memory 200600 kb
Host smart-e8652142-1abf-496d-a6db-2524e4ec31a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018392816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4018392816
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.242721583
Short name T224
Test name
Test status
Simulation time 3550118456 ps
CPU time 262.24 seconds
Started May 14 01:11:01 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 663980 kb
Host smart-5a9fcf94-3b2a-44bc-b162-5ed7aed00120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242721583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.242721583
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.744850789
Short name T306
Test name
Test status
Simulation time 3260439793 ps
CPU time 61.2 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:12:01 PM PDT 24
Peak memory 200704 kb
Host smart-1bb67fa7-bf4b-45f6-b6f7-6ca9ac5575a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744850789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.744850789
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4215167470
Short name T251
Test name
Test status
Simulation time 2708424787 ps
CPU time 5.04 seconds
Started May 14 01:10:52 PM PDT 24
Finished May 14 01:11:00 PM PDT 24
Peak memory 200668 kb
Host smart-e0e98b8d-0b24-4244-97d2-dc4a11aaf5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215167470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4215167470
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3997873372
Short name T3
Test name
Test status
Simulation time 170259475 ps
CPU time 0.99 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:11:01 PM PDT 24
Peak memory 199012 kb
Host smart-81578ef0-3f54-4121-9ac8-04c76397322c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997873372 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3997873372
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.538997194
Short name T41
Test name
Test status
Simulation time 21200910083 ps
CPU time 421.97 seconds
Started May 14 01:11:02 PM PDT 24
Finished May 14 01:18:08 PM PDT 24
Peak memory 200648 kb
Host smart-a1976bc2-9a94-484c-ac92-f5e88a5b141c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538997194 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.538997194
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.362869736
Short name T36
Test name
Test status
Simulation time 120049124 ps
CPU time 6.93 seconds
Started May 14 01:10:54 PM PDT 24
Finished May 14 01:11:03 PM PDT 24
Peak memory 200508 kb
Host smart-dadb711b-4b31-4b69-8166-1b92296f3fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362869736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.362869736
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3165161026
Short name T237
Test name
Test status
Simulation time 15875137 ps
CPU time 0.66 seconds
Started May 14 01:11:06 PM PDT 24
Finished May 14 01:11:10 PM PDT 24
Peak memory 196352 kb
Host smart-7119c23e-bdb3-4d40-add9-273a79df18af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165161026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3165161026
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1319826316
Short name T322
Test name
Test status
Simulation time 582966868 ps
CPU time 30.48 seconds
Started May 14 01:11:00 PM PDT 24
Finished May 14 01:11:34 PM PDT 24
Peak memory 200660 kb
Host smart-56866dff-5634-438f-9560-610b31cfe5f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319826316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1319826316
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1434019816
Short name T368
Test name
Test status
Simulation time 777193341 ps
CPU time 19.74 seconds
Started May 14 01:11:01 PM PDT 24
Finished May 14 01:11:24 PM PDT 24
Peak memory 200660 kb
Host smart-af7f84a1-3e22-4ae0-a63a-d8031d711d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434019816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1434019816
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.466570382
Short name T227
Test name
Test status
Simulation time 1334100087 ps
CPU time 351.14 seconds
Started May 14 01:10:57 PM PDT 24
Finished May 14 01:16:51 PM PDT 24
Peak memory 652048 kb
Host smart-8c8ac6be-9160-4be6-8a06-999b065b5357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466570382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.466570382
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2354279110
Short name T213
Test name
Test status
Simulation time 2623723777 ps
CPU time 34.83 seconds
Started May 14 01:10:58 PM PDT 24
Finished May 14 01:11:36 PM PDT 24
Peak memory 200952 kb
Host smart-046bb42d-57ed-4272-aabb-f8fe956c8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354279110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2354279110
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1255598595
Short name T202
Test name
Test status
Simulation time 1394895584 ps
CPU time 3.76 seconds
Started May 14 01:10:59 PM PDT 24
Finished May 14 01:11:06 PM PDT 24
Peak memory 200548 kb
Host smart-52b467df-6d0b-4e23-834a-2edf018d20a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255598595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1255598595
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1822759500
Short name T27
Test name
Test status
Simulation time 16124701048 ps
CPU time 80.75 seconds
Started May 14 01:11:10 PM PDT 24
Finished May 14 01:12:33 PM PDT 24
Peak memory 200636 kb
Host smart-b05101e2-ce14-4a84-bd66-7e643c553ca0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822759500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1822759500
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3865873377
Short name T230
Test name
Test status
Simulation time 28217849 ps
CPU time 1.04 seconds
Started May 14 01:11:07 PM PDT 24
Finished May 14 01:11:11 PM PDT 24
Peak memory 200180 kb
Host smart-37bb5219-f25e-4e8d-a937-8855fa5f6dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865873377 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3865873377
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1896917651
Short name T408
Test name
Test status
Simulation time 8442913957 ps
CPU time 495.79 seconds
Started May 14 01:11:02 PM PDT 24
Finished May 14 01:19:22 PM PDT 24
Peak memory 200652 kb
Host smart-b80c77d7-b525-411d-8206-47105eff2475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896917651 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1896917651
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2225550138
Short name T379
Test name
Test status
Simulation time 35035420 ps
CPU time 0.59 seconds
Started May 14 01:11:03 PM PDT 24
Finished May 14 01:11:08 PM PDT 24
Peak memory 196016 kb
Host smart-bac99c39-8fe7-42f4-9c3c-045fbb689be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225550138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2225550138
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1447398946
Short name T356
Test name
Test status
Simulation time 2941682201 ps
CPU time 38.75 seconds
Started May 14 01:11:04 PM PDT 24
Finished May 14 01:11:47 PM PDT 24
Peak memory 222288 kb
Host smart-529c15d4-d838-4147-80cb-f289d5c2abb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447398946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1447398946
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3564087211
Short name T106
Test name
Test status
Simulation time 10589684452 ps
CPU time 40.31 seconds
Started May 14 01:11:02 PM PDT 24
Finished May 14 01:11:46 PM PDT 24
Peak memory 200696 kb
Host smart-68d94a6f-9bf0-417f-b1e9-e895859960b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564087211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3564087211
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1883450626
Short name T172
Test name
Test status
Simulation time 376753264 ps
CPU time 78.22 seconds
Started May 14 01:11:03 PM PDT 24
Finished May 14 01:12:25 PM PDT 24
Peak memory 418400 kb
Host smart-882dd785-7956-42c1-805b-6e7a29918ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883450626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1883450626
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.354700577
Short name T330
Test name
Test status
Simulation time 28267220648 ps
CPU time 84.45 seconds
Started May 14 01:11:02 PM PDT 24
Finished May 14 01:12:30 PM PDT 24
Peak memory 200692 kb
Host smart-61fb2e7f-8aba-4504-9913-473278d8e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354700577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.354700577
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1690635481
Short name T373
Test name
Test status
Simulation time 871937072 ps
CPU time 5.57 seconds
Started May 14 01:11:03 PM PDT 24
Finished May 14 01:11:12 PM PDT 24
Peak memory 200576 kb
Host smart-cf60d256-1991-41a3-a819-2ce0fd3905e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690635481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1690635481
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3613138123
Short name T67
Test name
Test status
Simulation time 31094767 ps
CPU time 1.03 seconds
Started May 14 01:11:04 PM PDT 24
Finished May 14 01:11:09 PM PDT 24
Peak memory 200132 kb
Host smart-8c6ce8aa-9410-49f1-a84c-d45f9c3cd8aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613138123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3613138123
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1741167331
Short name T158
Test name
Test status
Simulation time 230059298101 ps
CPU time 475.6 seconds
Started May 14 01:11:00 PM PDT 24
Finished May 14 01:18:59 PM PDT 24
Peak memory 200664 kb
Host smart-a1756e02-d7fc-4244-9b74-4ccc0254ca0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741167331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1741167331
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3621975388
Short name T403
Test name
Test status
Simulation time 151826857 ps
CPU time 0.61 seconds
Started May 14 01:11:04 PM PDT 24
Finished May 14 01:11:08 PM PDT 24
Peak memory 196420 kb
Host smart-ac6c31e9-9c03-48dc-ba87-6102ef976a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621975388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3621975388
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2703009289
Short name T50
Test name
Test status
Simulation time 6003502239 ps
CPU time 61.71 seconds
Started May 14 01:11:03 PM PDT 24
Finished May 14 01:12:09 PM PDT 24
Peak memory 225280 kb
Host smart-c5a4b1b6-5d4e-4a1a-8d5b-88cae9c01728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703009289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2703009289
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3057503147
Short name T84
Test name
Test status
Simulation time 1124857207 ps
CPU time 57.42 seconds
Started May 14 01:11:06 PM PDT 24
Finished May 14 01:12:07 PM PDT 24
Peak memory 200592 kb
Host smart-46610d09-7bc5-4c45-8ce2-a622afe2618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057503147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3057503147
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.315243497
Short name T184
Test name
Test status
Simulation time 32748491059 ps
CPU time 885.7 seconds
Started May 14 01:11:06 PM PDT 24
Finished May 14 01:25:55 PM PDT 24
Peak memory 737804 kb
Host smart-d62d2e67-cc6d-4e60-9272-6e7360e4b629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315243497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.315243497
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1292216834
Short name T130
Test name
Test status
Simulation time 25668032549 ps
CPU time 124.34 seconds
Started May 14 01:11:05 PM PDT 24
Finished May 14 01:13:13 PM PDT 24
Peak memory 200716 kb
Host smart-a8890ecb-e65d-44fa-91be-db974455bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292216834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1292216834
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3026706193
Short name T204
Test name
Test status
Simulation time 1518520236 ps
CPU time 6.06 seconds
Started May 14 01:11:04 PM PDT 24
Finished May 14 01:11:14 PM PDT 24
Peak memory 200628 kb
Host smart-f9b679a2-0504-4007-b1da-d37b7c18aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026706193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3026706193
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.834705206
Short name T279
Test name
Test status
Simulation time 704509646 ps
CPU time 1.29 seconds
Started May 14 01:11:11 PM PDT 24
Finished May 14 01:11:14 PM PDT 24
Peak memory 200504 kb
Host smart-072676dd-eb25-4e6e-8329-e5967945b998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834705206 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.834705206
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1264590636
Short name T296
Test name
Test status
Simulation time 75803484899 ps
CPU time 487.24 seconds
Started May 14 01:11:01 PM PDT 24
Finished May 14 01:19:13 PM PDT 24
Peak memory 200656 kb
Host smart-56454949-20cc-4268-b1c5-bb6d61b54256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264590636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1264590636
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4236704163
Short name T282
Test name
Test status
Simulation time 27741918 ps
CPU time 0.63 seconds
Started May 14 01:11:17 PM PDT 24
Finished May 14 01:11:19 PM PDT 24
Peak memory 195980 kb
Host smart-0c536081-e4f6-4099-8014-10820b9efd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236704163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4236704163
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1583858904
Short name T410
Test name
Test status
Simulation time 843838848 ps
CPU time 25.5 seconds
Started May 14 01:11:23 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 241600 kb
Host smart-1308494a-e082-41fe-89b8-e3e4da311347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583858904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1583858904
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1095926997
Short name T200
Test name
Test status
Simulation time 8164829497 ps
CPU time 41.03 seconds
Started May 14 01:11:19 PM PDT 24
Finished May 14 01:12:02 PM PDT 24
Peak memory 200680 kb
Host smart-29139823-d77d-4035-b2b0-181f6edbc667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095926997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1095926997
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2184722068
Short name T37
Test name
Test status
Simulation time 449389041 ps
CPU time 80.87 seconds
Started May 14 01:11:19 PM PDT 24
Finished May 14 01:12:43 PM PDT 24
Peak memory 460372 kb
Host smart-8925702a-acaf-4a9d-919a-41be17273b4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184722068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2184722068
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_long_msg.422467194
Short name T104
Test name
Test status
Simulation time 11630093400 ps
CPU time 57.75 seconds
Started May 14 01:11:15 PM PDT 24
Finished May 14 01:12:14 PM PDT 24
Peak memory 200644 kb
Host smart-b8833714-213b-411f-941f-cea9fd479efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422467194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.422467194
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3912094183
Short name T404
Test name
Test status
Simulation time 86613553 ps
CPU time 2.94 seconds
Started May 14 01:11:23 PM PDT 24
Finished May 14 01:11:28 PM PDT 24
Peak memory 200640 kb
Host smart-d2b4d2e1-a882-47dd-8be1-ad35f0524d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912094183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3912094183
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.461799549
Short name T275
Test name
Test status
Simulation time 28112511 ps
CPU time 0.98 seconds
Started May 14 01:11:16 PM PDT 24
Finished May 14 01:11:18 PM PDT 24
Peak memory 198960 kb
Host smart-9a455dcc-8bea-4ce2-83f3-bfb51db3d635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461799549 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.461799549
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.956172626
Short name T327
Test name
Test status
Simulation time 38440726352 ps
CPU time 473.59 seconds
Started May 14 01:11:18 PM PDT 24
Finished May 14 01:19:13 PM PDT 24
Peak memory 200612 kb
Host smart-988d31a6-1a4d-4de8-9048-7fca8497c001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956172626 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.956172626
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2101623582
Short name T233
Test name
Test status
Simulation time 20048615 ps
CPU time 0.57 seconds
Started May 14 01:11:28 PM PDT 24
Finished May 14 01:11:32 PM PDT 24
Peak memory 197088 kb
Host smart-249a2c11-888f-4597-af27-97cf2a59c476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101623582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2101623582
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1486130626
Short name T46
Test name
Test status
Simulation time 1858233707 ps
CPU time 42.46 seconds
Started May 14 01:11:14 PM PDT 24
Finished May 14 01:11:57 PM PDT 24
Peak memory 215020 kb
Host smart-40fe5582-8472-4acc-9f22-5a54efd8ae54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486130626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1486130626
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1257082303
Short name T183
Test name
Test status
Simulation time 3093068379 ps
CPU time 35.39 seconds
Started May 14 01:11:15 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 200672 kb
Host smart-188f9038-585e-4358-94a8-ee22e6ae125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257082303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1257082303
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2533829380
Short name T405
Test name
Test status
Simulation time 12233828344 ps
CPU time 610.19 seconds
Started May 14 01:11:18 PM PDT 24
Finished May 14 01:21:31 PM PDT 24
Peak memory 722084 kb
Host smart-17bb23b2-cc8e-4877-b830-8cc2c1fe2b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533829380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2533829380
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3468863910
Short name T284
Test name
Test status
Simulation time 118593123 ps
CPU time 6.56 seconds
Started May 14 01:11:18 PM PDT 24
Finished May 14 01:11:26 PM PDT 24
Peak memory 200592 kb
Host smart-9112eb48-c6c0-4951-be6b-30ad46bcd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468863910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3468863910
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3551384266
Short name T392
Test name
Test status
Simulation time 331076900 ps
CPU time 1.5 seconds
Started May 14 01:11:21 PM PDT 24
Finished May 14 01:11:24 PM PDT 24
Peak memory 200760 kb
Host smart-0770af88-d2a7-4124-9a95-99a2034a43e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551384266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3551384266
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3058115953
Short name T72
Test name
Test status
Simulation time 2396810061 ps
CPU time 34.2 seconds
Started May 14 01:11:18 PM PDT 24
Finished May 14 01:11:55 PM PDT 24
Peak memory 200756 kb
Host smart-0622bc6b-c8a7-4746-a1b9-66dae7067bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058115953 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3058115953
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.73022980
Short name T450
Test name
Test status
Simulation time 272766404 ps
CPU time 1.2 seconds
Started May 14 01:11:18 PM PDT 24
Finished May 14 01:11:21 PM PDT 24
Peak memory 200320 kb
Host smart-417fdb19-31a6-43df-81fd-67f041cf42e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73022980 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_hmac_vectors.73022980
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1698080889
Short name T225
Test name
Test status
Simulation time 61225303536 ps
CPU time 546.56 seconds
Started May 14 01:11:17 PM PDT 24
Finished May 14 01:20:25 PM PDT 24
Peak memory 200696 kb
Host smart-0ceb3283-ad51-41f9-8581-374661a469de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698080889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1698080889
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2195099154
Short name T173
Test name
Test status
Simulation time 42569363 ps
CPU time 0.63 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:11:30 PM PDT 24
Peak memory 195296 kb
Host smart-fba7bf5b-f5ef-41db-9ed0-5c4997955113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195099154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2195099154
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3300867018
Short name T69
Test name
Test status
Simulation time 1889796458 ps
CPU time 49.26 seconds
Started May 14 01:11:25 PM PDT 24
Finished May 14 01:12:16 PM PDT 24
Peak memory 219040 kb
Host smart-367d127f-e738-4532-a317-fed99eaef896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300867018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3300867018
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1634536011
Short name T459
Test name
Test status
Simulation time 2199123707 ps
CPU time 10.6 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200644 kb
Host smart-ed69b7cb-f2d4-4b0a-8a91-5c44c217a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634536011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1634536011
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4072596265
Short name T81
Test name
Test status
Simulation time 1652995000 ps
CPU time 148.37 seconds
Started May 14 01:11:25 PM PDT 24
Finished May 14 01:13:56 PM PDT 24
Peak memory 381756 kb
Host smart-d5bb6466-5d03-418d-a4f0-a77c9c1aae85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072596265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4072596265
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4000877072
Short name T129
Test name
Test status
Simulation time 361402229 ps
CPU time 20.34 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:11:49 PM PDT 24
Peak memory 200540 kb
Host smart-9513ee8e-4d23-4fa2-ac0c-146439b5a1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000877072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4000877072
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2464590476
Short name T312
Test name
Test status
Simulation time 99950776 ps
CPU time 3.54 seconds
Started May 14 01:11:29 PM PDT 24
Finished May 14 01:11:37 PM PDT 24
Peak memory 200616 kb
Host smart-e7d39777-3ce4-4180-a548-075f3278cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464590476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2464590476
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.46500026
Short name T376
Test name
Test status
Simulation time 20745147071 ps
CPU time 122.69 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:13:43 PM PDT 24
Peak memory 225384 kb
Host smart-ab04b505-3f81-44ff-a117-959c565e38eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46500026 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.46500026
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1028572017
Short name T453
Test name
Test status
Simulation time 105650904 ps
CPU time 1.14 seconds
Started May 14 01:11:33 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200568 kb
Host smart-ddeeae57-9eba-4acf-8da1-f276af27fb1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028572017 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1028572017
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.4197765886
Short name T274
Test name
Test status
Simulation time 95401592157 ps
CPU time 426.69 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:18:47 PM PDT 24
Peak memory 200628 kb
Host smart-66d289cc-1cd5-499f-9db9-8c7c45a2975f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197765886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.4197765886
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4291283328
Short name T463
Test name
Test status
Simulation time 12703629 ps
CPU time 0.59 seconds
Started May 14 01:09:33 PM PDT 24
Finished May 14 01:09:34 PM PDT 24
Peak memory 196996 kb
Host smart-69a50114-79c2-4e86-af3f-852e883fb7e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291283328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4291283328
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1934986006
Short name T211
Test name
Test status
Simulation time 1544958913 ps
CPU time 41.53 seconds
Started May 14 01:09:31 PM PDT 24
Finished May 14 01:10:14 PM PDT 24
Peak memory 225180 kb
Host smart-94b43f23-73e7-4f3f-a6f3-20d099b9df08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934986006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1934986006
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3418166960
Short name T461
Test name
Test status
Simulation time 1111940700 ps
CPU time 13.45 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:09:54 PM PDT 24
Peak memory 200484 kb
Host smart-587b6daa-fbba-4ced-af23-7df1b96afbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418166960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3418166960
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2484927992
Short name T169
Test name
Test status
Simulation time 1609236246 ps
CPU time 154.35 seconds
Started May 14 01:09:37 PM PDT 24
Finished May 14 01:12:12 PM PDT 24
Peak memory 569384 kb
Host smart-02db2d98-8ab0-40e0-9efe-ffda0ef5a346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484927992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2484927992
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3161295578
Short name T259
Test name
Test status
Simulation time 30946936142 ps
CPU time 84.82 seconds
Started May 14 01:09:17 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 200708 kb
Host smart-c8e2f067-00e4-433e-96a6-71218fb044a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161295578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3161295578
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2616647479
Short name T38
Test name
Test status
Simulation time 103248241 ps
CPU time 0.86 seconds
Started May 14 01:09:32 PM PDT 24
Finished May 14 01:09:34 PM PDT 24
Peak memory 218840 kb
Host smart-9b6ce16d-0c47-4679-b23c-f70477d77661
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616647479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2616647479
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.875023768
Short name T341
Test name
Test status
Simulation time 101515888 ps
CPU time 1.65 seconds
Started May 14 01:09:18 PM PDT 24
Finished May 14 01:09:21 PM PDT 24
Peak memory 200560 kb
Host smart-a859ce79-681e-4bc5-b8f1-491b88722b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875023768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.875023768
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4154580693
Short name T124
Test name
Test status
Simulation time 9157579857 ps
CPU time 38.25 seconds
Started May 14 01:09:21 PM PDT 24
Finished May 14 01:10:00 PM PDT 24
Peak memory 200740 kb
Host smart-da29cd8e-5f09-4287-942c-d63e7f96d544
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154580693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4154580693
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.698625747
Short name T397
Test name
Test status
Simulation time 78881267 ps
CPU time 1.32 seconds
Started May 14 01:09:23 PM PDT 24
Finished May 14 01:09:25 PM PDT 24
Peak memory 200504 kb
Host smart-4332482f-8051-46b3-8419-5c385e2ce65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698625747 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.698625747
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3313410752
Short name T470
Test name
Test status
Simulation time 35547086879 ps
CPU time 499.17 seconds
Started May 14 01:09:23 PM PDT 24
Finished May 14 01:17:43 PM PDT 24
Peak memory 200524 kb
Host smart-cfc465a8-68d9-4ce4-ba25-da734cd9076d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313410752 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3313410752
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1045813796
Short name T317
Test name
Test status
Simulation time 38329009 ps
CPU time 0.63 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:11:31 PM PDT 24
Peak memory 196412 kb
Host smart-0f57d5e4-25f4-4fcb-a83e-4c41ae668398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045813796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1045813796
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3662833811
Short name T300
Test name
Test status
Simulation time 1926312428 ps
CPU time 26.73 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:11:57 PM PDT 24
Peak memory 216800 kb
Host smart-e99e457b-f5f0-4c0d-b53f-dd2097658cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662833811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3662833811
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4294014292
Short name T324
Test name
Test status
Simulation time 2070370594 ps
CPU time 56.11 seconds
Started May 14 01:11:28 PM PDT 24
Finished May 14 01:12:28 PM PDT 24
Peak memory 200628 kb
Host smart-28fcfc84-e5ee-4ebf-b8c2-c0be4b91a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294014292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4294014292
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.454414915
Short name T366
Test name
Test status
Simulation time 17847136924 ps
CPU time 884.15 seconds
Started May 14 01:11:29 PM PDT 24
Finished May 14 01:26:17 PM PDT 24
Peak memory 764476 kb
Host smart-25a95d3b-547e-4966-8ab1-f871d8cc74d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454414915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.454414915
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3544378194
Short name T462
Test name
Test status
Simulation time 20263323974 ps
CPU time 60.19 seconds
Started May 14 01:11:25 PM PDT 24
Finished May 14 01:12:27 PM PDT 24
Peak memory 200696 kb
Host smart-83dc1499-e1cf-49c7-b902-95e6eb502d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544378194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3544378194
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2880776213
Short name T473
Test name
Test status
Simulation time 211918898 ps
CPU time 2.92 seconds
Started May 14 01:11:32 PM PDT 24
Finished May 14 01:11:40 PM PDT 24
Peak memory 200508 kb
Host smart-1fe0e2e3-f1ce-408c-8ed8-4025cabe5f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880776213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2880776213
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1262968037
Short name T310
Test name
Test status
Simulation time 289571806813 ps
CPU time 545.93 seconds
Started May 14 01:11:25 PM PDT 24
Finished May 14 01:20:33 PM PDT 24
Peak memory 223580 kb
Host smart-b49e0802-bd24-43a3-b80f-d71e09fb5682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262968037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1262968037
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.766389966
Short name T371
Test name
Test status
Simulation time 33277462 ps
CPU time 1.29 seconds
Started May 14 01:11:23 PM PDT 24
Finished May 14 01:11:26 PM PDT 24
Peak memory 200568 kb
Host smart-83c9181f-5706-479e-8b81-74bf5f0de32e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766389966 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.766389966
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2000403617
Short name T391
Test name
Test status
Simulation time 30319908206 ps
CPU time 415.73 seconds
Started May 14 01:11:29 PM PDT 24
Finished May 14 01:18:30 PM PDT 24
Peak memory 200624 kb
Host smart-bcb9e64b-7d84-4c3c-b684-04a7f242a572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000403617 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2000403617
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3989555055
Short name T374
Test name
Test status
Simulation time 17759701 ps
CPU time 0.59 seconds
Started May 14 01:11:29 PM PDT 24
Finished May 14 01:11:35 PM PDT 24
Peak memory 196016 kb
Host smart-04e426d2-9c9d-4b46-bcd6-b149aa641a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989555055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3989555055
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1401045361
Short name T331
Test name
Test status
Simulation time 756136693 ps
CPU time 8.54 seconds
Started May 14 01:11:32 PM PDT 24
Finished May 14 01:11:46 PM PDT 24
Peak memory 208780 kb
Host smart-34a38b2b-0626-491b-8d7d-c3ce94f20428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401045361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1401045361
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.178618497
Short name T156
Test name
Test status
Simulation time 1677872219 ps
CPU time 8.15 seconds
Started May 14 01:11:28 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200556 kb
Host smart-5fd515fa-b46b-4ef3-8f06-5686d2a93aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178618497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.178618497
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2946676881
Short name T1
Test name
Test status
Simulation time 14882788716 ps
CPU time 639.74 seconds
Started May 14 01:11:27 PM PDT 24
Finished May 14 01:22:09 PM PDT 24
Peak memory 734236 kb
Host smart-470d20e9-f670-48ef-872e-d21fbc7af7af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946676881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2946676881
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2858348476
Short name T15
Test name
Test status
Simulation time 2910080966 ps
CPU time 39.45 seconds
Started May 14 01:11:26 PM PDT 24
Finished May 14 01:12:07 PM PDT 24
Peak memory 200712 kb
Host smart-f56bb588-10f6-47ce-b0cb-85cd667ceda4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858348476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2858348476
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3525603225
Short name T205
Test name
Test status
Simulation time 3818235853 ps
CPU time 115.17 seconds
Started May 14 01:11:34 PM PDT 24
Finished May 14 01:13:34 PM PDT 24
Peak memory 200680 kb
Host smart-d518a3f7-29b9-4e58-b7ad-d0bd5f0d6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525603225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3525603225
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1356918055
Short name T178
Test name
Test status
Simulation time 3054936410 ps
CPU time 5.55 seconds
Started May 14 01:11:26 PM PDT 24
Finished May 14 01:11:33 PM PDT 24
Peak memory 200692 kb
Host smart-338ffd61-d61a-47aa-b6cb-68608496b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356918055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1356918055
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1305521903
Short name T155
Test name
Test status
Simulation time 60656930 ps
CPU time 1.12 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:11:40 PM PDT 24
Peak memory 200612 kb
Host smart-41101fe7-9937-4baa-b770-bd11c2205b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305521903 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1305521903
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3719006506
Short name T336
Test name
Test status
Simulation time 24820841457 ps
CPU time 460.53 seconds
Started May 14 01:11:28 PM PDT 24
Finished May 14 01:19:12 PM PDT 24
Peak memory 200556 kb
Host smart-782622ac-b946-4a4c-8cd6-65429e90cf85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719006506 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3719006506
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3411448980
Short name T133
Test name
Test status
Simulation time 85461037 ps
CPU time 0.56 seconds
Started May 14 01:11:31 PM PDT 24
Finished May 14 01:11:36 PM PDT 24
Peak memory 195348 kb
Host smart-1bef0e96-8a64-4249-b76e-764f5b1d944e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411448980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3411448980
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1731592757
Short name T301
Test name
Test status
Simulation time 1450169489 ps
CPU time 7.76 seconds
Started May 14 01:11:30 PM PDT 24
Finished May 14 01:11:43 PM PDT 24
Peak memory 216640 kb
Host smart-35329123-75fb-4eeb-8469-e0cedf78405f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731592757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1731592757
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1499971088
Short name T468
Test name
Test status
Simulation time 5602209140 ps
CPU time 52.19 seconds
Started May 14 01:11:30 PM PDT 24
Finished May 14 01:12:27 PM PDT 24
Peak memory 200760 kb
Host smart-5f363173-13d9-4103-adc7-a4a877d175e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499971088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1499971088
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2601933501
Short name T137
Test name
Test status
Simulation time 363607972 ps
CPU time 44.94 seconds
Started May 14 01:11:30 PM PDT 24
Finished May 14 01:12:20 PM PDT 24
Peak memory 309836 kb
Host smart-33cfa68c-797a-43d1-906f-99745f2f7464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601933501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2601933501
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1701159698
Short name T170
Test name
Test status
Simulation time 140950032 ps
CPU time 8.04 seconds
Started May 14 01:11:30 PM PDT 24
Finished May 14 01:11:43 PM PDT 24
Peak memory 200592 kb
Host smart-0a93368d-dab4-4304-917f-15fe6efc0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701159698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1701159698
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1523656521
Short name T197
Test name
Test status
Simulation time 1250551287 ps
CPU time 5.25 seconds
Started May 14 01:11:29 PM PDT 24
Finished May 14 01:11:38 PM PDT 24
Peak memory 200548 kb
Host smart-2e5b4df3-9fa6-4a3a-ad00-5eeb86cb8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523656521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1523656521
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1475435996
Short name T162
Test name
Test status
Simulation time 76153033 ps
CPU time 0.96 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:11:41 PM PDT 24
Peak memory 199352 kb
Host smart-2d2f79cc-3a5d-4d2f-b52e-a17456c90d82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475435996 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1475435996
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2518489214
Short name T249
Test name
Test status
Simulation time 29581741247 ps
CPU time 512.58 seconds
Started May 14 01:11:34 PM PDT 24
Finished May 14 01:20:11 PM PDT 24
Peak memory 200636 kb
Host smart-0c089ed0-9c54-481c-8cfd-8194ce2dbea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518489214 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2518489214
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2823483024
Short name T418
Test name
Test status
Simulation time 28245401 ps
CPU time 0.59 seconds
Started May 14 01:11:33 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 196424 kb
Host smart-7e73e70a-c2cd-441f-b770-5eeb8d3d52c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823483024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2823483024
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1043836763
Short name T281
Test name
Test status
Simulation time 1388201154 ps
CPU time 19.83 seconds
Started May 14 01:11:34 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 225776 kb
Host smart-bc254529-2f88-40a5-a628-8103a9dcb594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043836763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1043836763
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1974155943
Short name T293
Test name
Test status
Simulation time 10492489018 ps
CPU time 34.12 seconds
Started May 14 01:11:37 PM PDT 24
Finished May 14 01:12:15 PM PDT 24
Peak memory 200716 kb
Host smart-669e8716-a4c3-4cdf-b41b-2a521433dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974155943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1974155943
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2953145148
Short name T308
Test name
Test status
Simulation time 18535125015 ps
CPU time 1237.09 seconds
Started May 14 01:11:44 PM PDT 24
Finished May 14 01:32:23 PM PDT 24
Peak memory 759224 kb
Host smart-7b52b1ed-c409-4838-8be6-838e1d51c5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953145148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2953145148
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3871964392
Short name T260
Test name
Test status
Simulation time 391693848 ps
CPU time 21.22 seconds
Started May 14 01:11:41 PM PDT 24
Finished May 14 01:12:04 PM PDT 24
Peak memory 200480 kb
Host smart-b0067e9e-fe6b-45e9-a43b-cb93752f2c4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871964392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3871964392
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.589930405
Short name T65
Test name
Test status
Simulation time 576834991 ps
CPU time 6.13 seconds
Started May 14 01:11:31 PM PDT 24
Finished May 14 01:11:42 PM PDT 24
Peak memory 200480 kb
Host smart-3d9b8267-bc65-4467-9ad2-c227d13bb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589930405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.589930405
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.974418771
Short name T151
Test name
Test status
Simulation time 206546997 ps
CPU time 1.99 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 200644 kb
Host smart-639dec41-e925-4790-b457-dacafef279b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974418771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.974418771
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.4001949020
Short name T177
Test name
Test status
Simulation time 197210055 ps
CPU time 1.18 seconds
Started May 14 01:11:32 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200444 kb
Host smart-e3cd8d19-dfc3-483d-9a4b-99dc50c1847c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001949020 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.4001949020
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3299399589
Short name T413
Test name
Test status
Simulation time 34429577295 ps
CPU time 503.18 seconds
Started May 14 01:11:36 PM PDT 24
Finished May 14 01:20:04 PM PDT 24
Peak memory 200656 kb
Host smart-8973f373-ff37-4480-a45c-8096e1ccc7d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299399589 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3299399589
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2438475558
Short name T223
Test name
Test status
Simulation time 13180870 ps
CPU time 0.56 seconds
Started May 14 01:11:39 PM PDT 24
Finished May 14 01:11:43 PM PDT 24
Peak memory 195272 kb
Host smart-70c1a7ae-3e2a-4ffd-92b0-c917dc8a7fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438475558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2438475558
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.58953109
Short name T7
Test name
Test status
Simulation time 2374767567 ps
CPU time 59.43 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:12:39 PM PDT 24
Peak memory 230836 kb
Host smart-fba3dc30-d6f3-492c-98aa-94e61c889f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58953109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.58953109
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2224285254
Short name T415
Test name
Test status
Simulation time 7278262828 ps
CPU time 18.07 seconds
Started May 14 01:11:43 PM PDT 24
Finished May 14 01:12:03 PM PDT 24
Peak memory 200688 kb
Host smart-5b11c74f-9839-478a-bed5-228a24d57e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224285254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2224285254
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3108220768
Short name T448
Test name
Test status
Simulation time 2206780957 ps
CPU time 544.13 seconds
Started May 14 01:11:37 PM PDT 24
Finished May 14 01:20:45 PM PDT 24
Peak memory 668532 kb
Host smart-f28c5d78-a3a8-455e-8a93-9f2fa0d02b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108220768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3108220768
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3295298662
Short name T131
Test name
Test status
Simulation time 1398940075 ps
CPU time 81.34 seconds
Started May 14 01:11:32 PM PDT 24
Finished May 14 01:12:59 PM PDT 24
Peak memory 200536 kb
Host smart-c4454679-b4a6-4af7-aeb4-fdac7482e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295298662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3295298662
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1578483783
Short name T141
Test name
Test status
Simulation time 957783882 ps
CPU time 6.67 seconds
Started May 14 01:11:35 PM PDT 24
Finished May 14 01:11:47 PM PDT 24
Peak memory 200620 kb
Host smart-08ff5927-86fc-4749-9309-feae7e9fadd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578483783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1578483783
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1910132103
Short name T447
Test name
Test status
Simulation time 99255449 ps
CPU time 1.3 seconds
Started May 14 01:11:39 PM PDT 24
Finished May 14 01:11:44 PM PDT 24
Peak memory 200708 kb
Host smart-4f80205f-aada-4e62-b9b7-5dc415ec37ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910132103 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1910132103
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.616930084
Short name T147
Test name
Test status
Simulation time 26772873405 ps
CPU time 466.23 seconds
Started May 14 01:11:40 PM PDT 24
Finished May 14 01:19:29 PM PDT 24
Peak memory 200636 kb
Host smart-10df71e0-3dbe-442e-b890-830eb6b60426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616930084 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.616930084
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.924421033
Short name T407
Test name
Test status
Simulation time 58111543 ps
CPU time 0.6 seconds
Started May 14 01:11:42 PM PDT 24
Finished May 14 01:11:45 PM PDT 24
Peak memory 196356 kb
Host smart-8b1cc8e6-ba25-470f-9cc6-54348768eb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924421033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.924421033
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4151662495
Short name T326
Test name
Test status
Simulation time 1975826511 ps
CPU time 53.76 seconds
Started May 14 01:11:51 PM PDT 24
Finished May 14 01:12:48 PM PDT 24
Peak memory 222100 kb
Host smart-44957795-9ea4-410b-803e-3d959ff9e883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151662495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4151662495
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.187576722
Short name T396
Test name
Test status
Simulation time 2390127730 ps
CPU time 10.27 seconds
Started May 14 01:11:49 PM PDT 24
Finished May 14 01:12:02 PM PDT 24
Peak memory 200700 kb
Host smart-449bb2d2-b118-43ab-8462-8ca0cae4d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187576722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.187576722
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1096238790
Short name T64
Test name
Test status
Simulation time 8075701732 ps
CPU time 1300.53 seconds
Started May 14 01:11:48 PM PDT 24
Finished May 14 01:33:32 PM PDT 24
Peak memory 756392 kb
Host smart-27f96be5-71c2-4b23-bf3d-ae7a6c882b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096238790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1096238790
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2483902887
Short name T375
Test name
Test status
Simulation time 19439725733 ps
CPU time 56.59 seconds
Started May 14 01:11:47 PM PDT 24
Finished May 14 01:12:46 PM PDT 24
Peak memory 200680 kb
Host smart-e34a390e-3cae-4af1-86f7-53554eb2d7e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483902887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2483902887
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.659905101
Short name T191
Test name
Test status
Simulation time 3281758931 ps
CPU time 92.34 seconds
Started May 14 01:11:47 PM PDT 24
Finished May 14 01:13:22 PM PDT 24
Peak memory 200772 kb
Host smart-62ae8737-1884-4247-8239-4bbd469cc3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659905101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.659905101
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3547572752
Short name T175
Test name
Test status
Simulation time 188688384 ps
CPU time 1.97 seconds
Started May 14 01:11:37 PM PDT 24
Finished May 14 01:11:43 PM PDT 24
Peak memory 200604 kb
Host smart-6957e5bb-87e2-4ab1-aa81-0cf14139ac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547572752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3547572752
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2263871411
Short name T201
Test name
Test status
Simulation time 27590629 ps
CPU time 0.99 seconds
Started May 14 01:11:42 PM PDT 24
Finished May 14 01:11:45 PM PDT 24
Peak memory 200336 kb
Host smart-335c4e58-c91c-4ac8-9717-b686b863d256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263871411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2263871411
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.506267831
Short name T359
Test name
Test status
Simulation time 41261916515 ps
CPU time 546.6 seconds
Started May 14 01:11:48 PM PDT 24
Finished May 14 01:20:57 PM PDT 24
Peak memory 200560 kb
Host smart-1cc621e7-4805-42f9-9311-07a81392b56e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506267831 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.506267831
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3044948437
Short name T228
Test name
Test status
Simulation time 40108766 ps
CPU time 0.56 seconds
Started May 14 01:11:42 PM PDT 24
Finished May 14 01:11:45 PM PDT 24
Peak memory 196372 kb
Host smart-9cbefa3c-40b4-4edc-b084-e3d6e73ee6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044948437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3044948437
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3000009252
Short name T48
Test name
Test status
Simulation time 143156824 ps
CPU time 6.97 seconds
Started May 14 01:11:42 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 208832 kb
Host smart-58f51bac-595f-49d0-8af1-c56fc41d541f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000009252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3000009252
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.521810309
Short name T299
Test name
Test status
Simulation time 1699356191 ps
CPU time 41.36 seconds
Started May 14 01:11:49 PM PDT 24
Finished May 14 01:12:33 PM PDT 24
Peak memory 200604 kb
Host smart-1fc01849-ebfc-46c7-9dbe-75e448a5cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521810309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.521810309
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3103249166
Short name T256
Test name
Test status
Simulation time 636985900 ps
CPU time 76.98 seconds
Started May 14 01:11:45 PM PDT 24
Finished May 14 01:13:04 PM PDT 24
Peak memory 271256 kb
Host smart-ebe3d03b-fc52-499d-933b-2f7736a606eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103249166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3103249166
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.804436013
Short name T194
Test name
Test status
Simulation time 6438809351 ps
CPU time 43.32 seconds
Started May 14 01:11:43 PM PDT 24
Finished May 14 01:12:29 PM PDT 24
Peak memory 200652 kb
Host smart-39295f67-0cdf-4a28-902f-7c86a0ee6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804436013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.804436013
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1675795363
Short name T167
Test name
Test status
Simulation time 166626756 ps
CPU time 5.48 seconds
Started May 14 01:11:47 PM PDT 24
Finished May 14 01:11:55 PM PDT 24
Peak memory 200612 kb
Host smart-a6c4068b-059c-407c-acfb-c1d151ce2593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675795363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1675795363
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3671618447
Short name T451
Test name
Test status
Simulation time 339142808 ps
CPU time 1.34 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 200632 kb
Host smart-9b5cebbc-7d9d-41b6-a07d-0a8756ea64f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671618447 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3671618447
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.4040969762
Short name T369
Test name
Test status
Simulation time 8975787911 ps
CPU time 506.55 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:20:22 PM PDT 24
Peak memory 200684 kb
Host smart-f401079b-b6de-4df8-8a6d-251993f0b596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040969762 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.4040969762
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3728508019
Short name T280
Test name
Test status
Simulation time 21985697 ps
CPU time 0.59 seconds
Started May 14 01:11:53 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 195308 kb
Host smart-f31606fa-c159-4400-99ef-452f8cec59c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728508019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3728508019
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4020834412
Short name T47
Test name
Test status
Simulation time 870327083 ps
CPU time 48.65 seconds
Started May 14 01:11:42 PM PDT 24
Finished May 14 01:12:33 PM PDT 24
Peak memory 216916 kb
Host smart-8e22c5b5-0ca4-4855-8b0c-8ba8ed328824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020834412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4020834412
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3014334716
Short name T135
Test name
Test status
Simulation time 173825022 ps
CPU time 4.62 seconds
Started May 14 01:11:51 PM PDT 24
Finished May 14 01:12:00 PM PDT 24
Peak memory 200592 kb
Host smart-948e2dfb-91f5-42a4-9b97-f163857801c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014334716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3014334716
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1023867201
Short name T283
Test name
Test status
Simulation time 18846916963 ps
CPU time 195.21 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 361776 kb
Host smart-48380a4d-26fa-4e6f-b3bc-56aa3cd6f27c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023867201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1023867201
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.297432468
Short name T128
Test name
Test status
Simulation time 680411135 ps
CPU time 2.75 seconds
Started May 14 01:11:44 PM PDT 24
Finished May 14 01:11:50 PM PDT 24
Peak memory 200556 kb
Host smart-2692513c-408d-424c-a31c-878dffd86282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297432468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.297432468
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2289405344
Short name T247
Test name
Test status
Simulation time 152955077 ps
CPU time 2.67 seconds
Started May 14 01:11:46 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 200576 kb
Host smart-8f9b4630-d480-4b2d-8bd9-7a684117b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289405344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2289405344
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2553510247
Short name T83
Test name
Test status
Simulation time 197013199 ps
CPU time 1.03 seconds
Started May 14 01:11:50 PM PDT 24
Finished May 14 01:11:55 PM PDT 24
Peak memory 200048 kb
Host smart-db660857-210a-468a-bc2e-1c4fb57c539d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553510247 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2553510247
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1839757698
Short name T313
Test name
Test status
Simulation time 39382094364 ps
CPU time 512.61 seconds
Started May 14 01:12:00 PM PDT 24
Finished May 14 01:20:35 PM PDT 24
Peak memory 200708 kb
Host smart-6d691949-54d8-45c7-bbd8-15ce2f596574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839757698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1839757698
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.928277316
Short name T20
Test name
Test status
Simulation time 13004083 ps
CPU time 0.58 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:11:56 PM PDT 24
Peak memory 197092 kb
Host smart-a040b249-dc8d-4cbe-b824-9de584294f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928277316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.928277316
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.438615701
Short name T340
Test name
Test status
Simulation time 1258677772 ps
CPU time 4.69 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:12:00 PM PDT 24
Peak memory 216472 kb
Host smart-d88addef-cf38-4512-8670-a824d078c9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438615701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.438615701
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3880588975
Short name T179
Test name
Test status
Simulation time 6331337756 ps
CPU time 57.27 seconds
Started May 14 01:12:00 PM PDT 24
Finished May 14 01:12:59 PM PDT 24
Peak memory 200776 kb
Host smart-a8e289fb-d5de-42de-b39c-bfbc214f76f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880588975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3880588975
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2667691122
Short name T440
Test name
Test status
Simulation time 3973168908 ps
CPU time 53.22 seconds
Started May 14 01:11:55 PM PDT 24
Finished May 14 01:12:52 PM PDT 24
Peak memory 200716 kb
Host smart-4b79acd3-a7c2-4078-ba00-c41b3c0c20dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667691122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2667691122
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.258401667
Short name T400
Test name
Test status
Simulation time 30207238 ps
CPU time 1.17 seconds
Started May 14 01:11:54 PM PDT 24
Finished May 14 01:11:59 PM PDT 24
Peak memory 200476 kb
Host smart-4638eee8-aac2-4b58-83ec-c9eee8847f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258401667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.258401667
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1790711594
Short name T149
Test name
Test status
Simulation time 2050728442 ps
CPU time 466.27 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:19:42 PM PDT 24
Peak memory 644756 kb
Host smart-ee67eca3-c5c3-406f-a384-b929b0739c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790711594 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1790711594
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2319528170
Short name T361
Test name
Test status
Simulation time 1351758558 ps
CPU time 1.39 seconds
Started May 14 01:11:53 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 199688 kb
Host smart-25d5d048-539d-4940-9817-0d9d2cd747ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319528170 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2319528170
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1432914000
Short name T222
Test name
Test status
Simulation time 8929433332 ps
CPU time 490.65 seconds
Started May 14 01:11:49 PM PDT 24
Finished May 14 01:20:03 PM PDT 24
Peak memory 200720 kb
Host smart-902f0080-4fb5-46b6-9b9c-2ebec0ffd89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432914000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1432914000
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1501630800
Short name T394
Test name
Test status
Simulation time 22439694 ps
CPU time 0.62 seconds
Started May 14 01:11:53 PM PDT 24
Finished May 14 01:11:57 PM PDT 24
Peak memory 197120 kb
Host smart-b75da324-b2c8-4e2c-b43e-a71ff1df8c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501630800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1501630800
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2874507427
Short name T455
Test name
Test status
Simulation time 212129825 ps
CPU time 10.35 seconds
Started May 14 01:11:52 PM PDT 24
Finished May 14 01:12:06 PM PDT 24
Peak memory 200596 kb
Host smart-d770fc26-b8e2-4c78-88c3-d5988f78e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874507427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2874507427
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2652801976
Short name T182
Test name
Test status
Simulation time 3859374719 ps
CPU time 998.2 seconds
Started May 14 01:11:54 PM PDT 24
Finished May 14 01:28:36 PM PDT 24
Peak memory 705804 kb
Host smart-b024b51b-a641-4e70-90fd-249089f3e7a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652801976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2652801976
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.939227444
Short name T203
Test name
Test status
Simulation time 1618152798 ps
CPU time 16.53 seconds
Started May 14 01:11:54 PM PDT 24
Finished May 14 01:12:14 PM PDT 24
Peak memory 200592 kb
Host smart-15bd0cfa-fbcd-4610-bc91-20535808294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939227444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.939227444
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1111957319
Short name T319
Test name
Test status
Simulation time 448722428 ps
CPU time 3.9 seconds
Started May 14 01:11:50 PM PDT 24
Finished May 14 01:11:57 PM PDT 24
Peak memory 200564 kb
Host smart-5566214c-966b-44c7-a037-70c5e1ddf952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111957319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1111957319
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1812279647
Short name T112
Test name
Test status
Simulation time 1466937163 ps
CPU time 51.31 seconds
Started May 14 01:12:04 PM PDT 24
Finished May 14 01:12:57 PM PDT 24
Peak memory 208844 kb
Host smart-7c0bf6b9-b02b-4193-906b-12109998e125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812279647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1812279647
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3212576952
Short name T304
Test name
Test status
Simulation time 102585518 ps
CPU time 0.98 seconds
Started May 14 01:11:53 PM PDT 24
Finished May 14 01:11:58 PM PDT 24
Peak memory 199920 kb
Host smart-8f83bca6-b3c6-48dd-a2bb-c41819c7a09b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212576952 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3212576952
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.3186733283
Short name T208
Test name
Test status
Simulation time 148568739891 ps
CPU time 489.92 seconds
Started May 14 01:11:50 PM PDT 24
Finished May 14 01:20:03 PM PDT 24
Peak memory 200872 kb
Host smart-c7db5114-4e60-44c5-83c3-78bfb9c399d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186733283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.3186733283
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3954362432
Short name T34
Test name
Test status
Simulation time 832011308 ps
CPU time 3.93 seconds
Started May 14 01:11:56 PM PDT 24
Finished May 14 01:12:03 PM PDT 24
Peak memory 200456 kb
Host smart-dd25460d-b68c-408e-b779-f0075b5cae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954362432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3954362432
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1990251129
Short name T168
Test name
Test status
Simulation time 39639836 ps
CPU time 0.63 seconds
Started May 14 01:09:34 PM PDT 24
Finished May 14 01:09:36 PM PDT 24
Peak memory 196360 kb
Host smart-cb2f7c21-3906-4636-ad1b-d7d2c264a359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990251129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1990251129
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2974509485
Short name T252
Test name
Test status
Simulation time 3267186724 ps
CPU time 40.99 seconds
Started May 14 01:09:35 PM PDT 24
Finished May 14 01:10:18 PM PDT 24
Peak memory 227348 kb
Host smart-bffa239d-0f9a-44f3-bba1-4c4ecea90cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974509485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2974509485
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2309693216
Short name T270
Test name
Test status
Simulation time 12128095285 ps
CPU time 45.65 seconds
Started May 14 01:09:40 PM PDT 24
Finished May 14 01:10:27 PM PDT 24
Peak memory 200696 kb
Host smart-70eb3ecc-7c12-4c71-9c07-5a63622d397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309693216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2309693216
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4204297595
Short name T294
Test name
Test status
Simulation time 3073666033 ps
CPU time 852 seconds
Started May 14 01:09:26 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 749772 kb
Host smart-d05fa5f9-a9e5-4dd7-81da-8626f681f98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204297595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4204297595
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.139535970
Short name T217
Test name
Test status
Simulation time 6860755531 ps
CPU time 66.04 seconds
Started May 14 01:09:24 PM PDT 24
Finished May 14 01:10:31 PM PDT 24
Peak memory 200724 kb
Host smart-63decb81-ba14-49e1-8c56-c178acb656cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139535970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.139535970
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.973074247
Short name T231
Test name
Test status
Simulation time 131975589 ps
CPU time 4.18 seconds
Started May 14 01:09:24 PM PDT 24
Finished May 14 01:09:29 PM PDT 24
Peak memory 200628 kb
Host smart-99c5969a-823b-47ad-8e58-38d11a69c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973074247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.973074247
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2947240736
Short name T439
Test name
Test status
Simulation time 73678644 ps
CPU time 1.3 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:09:41 PM PDT 24
Peak memory 200504 kb
Host smart-7d1499c6-95a0-4412-a64d-5ba6271cf9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947240736 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2947240736
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1166776226
Short name T160
Test name
Test status
Simulation time 141815384716 ps
CPU time 447.39 seconds
Started May 14 01:09:29 PM PDT 24
Finished May 14 01:16:58 PM PDT 24
Peak memory 200644 kb
Host smart-6f2855e2-f594-404f-852a-ffb2300dc0ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166776226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1166776226
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.541469404
Short name T321
Test name
Test status
Simulation time 19436058 ps
CPU time 0.59 seconds
Started May 14 01:09:35 PM PDT 24
Finished May 14 01:09:37 PM PDT 24
Peak memory 196196 kb
Host smart-1b9b684a-4695-4beb-a9e3-17e71f967106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541469404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.541469404
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1763725321
Short name T148
Test name
Test status
Simulation time 184919727 ps
CPU time 2.29 seconds
Started May 14 01:09:35 PM PDT 24
Finished May 14 01:09:38 PM PDT 24
Peak memory 200420 kb
Host smart-b73074da-381a-49fe-af62-b5f09686810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763725321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1763725321
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3476225706
Short name T8
Test name
Test status
Simulation time 3206066063 ps
CPU time 818.49 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:23:18 PM PDT 24
Peak memory 702120 kb
Host smart-1c9747cb-1815-422e-9d30-ef66aa7185f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476225706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3476225706
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1274720577
Short name T24
Test name
Test status
Simulation time 2531375600 ps
CPU time 39.09 seconds
Started May 14 01:09:29 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 200672 kb
Host smart-447397d6-d6c9-4f1c-847f-7ff499c71db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274720577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1274720577
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3595690051
Short name T465
Test name
Test status
Simulation time 325362084 ps
CPU time 2.81 seconds
Started May 14 01:09:36 PM PDT 24
Finished May 14 01:09:40 PM PDT 24
Peak memory 200652 kb
Host smart-e92ca79a-7546-4428-bac8-7377ab61f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595690051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3595690051
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2801464515
Short name T62
Test name
Test status
Simulation time 244555914 ps
CPU time 1.34 seconds
Started May 14 01:09:35 PM PDT 24
Finished May 14 01:09:37 PM PDT 24
Peak memory 200240 kb
Host smart-3c68748f-d3b8-4de9-b59f-e4119a9e9911
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801464515 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2801464515
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1841858059
Short name T388
Test name
Test status
Simulation time 7632327317 ps
CPU time 431 seconds
Started May 14 01:09:30 PM PDT 24
Finished May 14 01:16:42 PM PDT 24
Peak memory 200620 kb
Host smart-4955843c-b948-4a38-a39a-877cc0209426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841858059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1841858059
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.396631830
Short name T232
Test name
Test status
Simulation time 54968319 ps
CPU time 0.56 seconds
Started May 14 01:09:43 PM PDT 24
Finished May 14 01:09:45 PM PDT 24
Peak memory 195304 kb
Host smart-4f9e2a50-4db2-43cc-83c9-2b3e346f5c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396631830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.396631830
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4189312702
Short name T45
Test name
Test status
Simulation time 4418182377 ps
CPU time 42.5 seconds
Started May 14 01:09:40 PM PDT 24
Finished May 14 01:10:24 PM PDT 24
Peak memory 214744 kb
Host smart-ca2b4287-0c6c-498e-a1c4-074da7afb68c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189312702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4189312702
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.147866841
Short name T68
Test name
Test status
Simulation time 1006837459 ps
CPU time 174.59 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:12:35 PM PDT 24
Peak memory 613372 kb
Host smart-0f3c473b-77f2-48c3-833c-b9ab6f29045e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147866841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.147866841
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2676156250
Short name T311
Test name
Test status
Simulation time 2409479052 ps
CPU time 43.51 seconds
Started May 14 01:09:27 PM PDT 24
Finished May 14 01:10:12 PM PDT 24
Peak memory 200676 kb
Host smart-3d116c14-674d-44c3-8f70-3d588d97df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676156250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2676156250
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2998137258
Short name T444
Test name
Test status
Simulation time 714993731 ps
CPU time 6.07 seconds
Started May 14 01:09:24 PM PDT 24
Finished May 14 01:09:31 PM PDT 24
Peak memory 200612 kb
Host smart-841d381a-afef-4994-aad1-993936886ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998137258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2998137258
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2240240625
Short name T430
Test name
Test status
Simulation time 202990002 ps
CPU time 1.32 seconds
Started May 14 01:09:34 PM PDT 24
Finished May 14 01:09:37 PM PDT 24
Peak memory 200664 kb
Host smart-2f01ce8b-c606-4357-9347-fb78b731e872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240240625 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2240240625
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.924774677
Short name T289
Test name
Test status
Simulation time 79393254719 ps
CPU time 454.62 seconds
Started May 14 01:09:45 PM PDT 24
Finished May 14 01:17:21 PM PDT 24
Peak memory 200628 kb
Host smart-1af18256-35d7-4079-bb48-ebebefffb144
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924774677 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.924774677
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4058607575
Short name T198
Test name
Test status
Simulation time 33649656 ps
CPU time 0.56 seconds
Started May 14 01:09:38 PM PDT 24
Finished May 14 01:09:40 PM PDT 24
Peak memory 196092 kb
Host smart-5a954a69-2a5b-4cca-9cf6-1486e263e6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058607575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4058607575
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.328316311
Short name T387
Test name
Test status
Simulation time 615021325 ps
CPU time 3.12 seconds
Started May 14 01:09:39 PM PDT 24
Finished May 14 01:09:45 PM PDT 24
Peak memory 208616 kb
Host smart-a89b7896-06e9-413a-b89c-d00f311dea15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328316311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.328316311
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4287628486
Short name T110
Test name
Test status
Simulation time 5710437768 ps
CPU time 75.05 seconds
Started May 14 01:09:55 PM PDT 24
Finished May 14 01:11:14 PM PDT 24
Peak memory 200744 kb
Host smart-927c78c8-5edb-4416-951d-2774b7ced100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287628486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4287628486
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2576288069
Short name T445
Test name
Test status
Simulation time 8722467545 ps
CPU time 1249.78 seconds
Started May 14 01:09:34 PM PDT 24
Finished May 14 01:30:26 PM PDT 24
Peak memory 737316 kb
Host smart-76c0a7b1-0bc6-473b-85cc-a831fb30dac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576288069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2576288069
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3094556046
Short name T320
Test name
Test status
Simulation time 5708119901 ps
CPU time 103.27 seconds
Started May 14 01:09:44 PM PDT 24
Finished May 14 01:11:29 PM PDT 24
Peak memory 200640 kb
Host smart-abdc4a43-b7a4-4573-885e-71ccb7676e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094556046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3094556046
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.317185666
Short name T263
Test name
Test status
Simulation time 199840742 ps
CPU time 3.41 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:10:04 PM PDT 24
Peak memory 200504 kb
Host smart-3b15927e-f28f-42f4-ba37-229922cf60cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317185666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.317185666
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.511139478
Short name T142
Test name
Test status
Simulation time 90926865 ps
CPU time 1.37 seconds
Started May 14 01:09:41 PM PDT 24
Finished May 14 01:09:44 PM PDT 24
Peak memory 200540 kb
Host smart-1974bbd1-b05a-4764-837d-052350030640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511139478 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.511139478
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1806407141
Short name T435
Test name
Test status
Simulation time 73484641073 ps
CPU time 408.21 seconds
Started May 14 01:09:47 PM PDT 24
Finished May 14 01:16:37 PM PDT 24
Peak memory 200628 kb
Host smart-c1e7c5c1-909d-4918-abe5-f21a6f440829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806407141 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1806407141
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1066648005
Short name T454
Test name
Test status
Simulation time 15222924 ps
CPU time 0.62 seconds
Started May 14 01:09:49 PM PDT 24
Finished May 14 01:09:52 PM PDT 24
Peak memory 197076 kb
Host smart-339199e6-2860-4177-ba88-a81d2bb7daf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066648005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1066648005
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2259117373
Short name T49
Test name
Test status
Simulation time 509432910 ps
CPU time 27.18 seconds
Started May 14 01:09:46 PM PDT 24
Finished May 14 01:10:16 PM PDT 24
Peak memory 220320 kb
Host smart-7b2bdafb-2656-4476-a84d-8cef433cc62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259117373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2259117373
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2912185275
Short name T196
Test name
Test status
Simulation time 65097757 ps
CPU time 0.67 seconds
Started May 14 01:09:35 PM PDT 24
Finished May 14 01:09:37 PM PDT 24
Peak memory 196908 kb
Host smart-aece8226-f91f-4d41-8836-f1b1e950b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912185275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2912185275
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.743644368
Short name T399
Test name
Test status
Simulation time 1928558734 ps
CPU time 378.76 seconds
Started May 14 01:09:39 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 641892 kb
Host smart-0fcf90be-f07e-473c-8817-005c43152ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743644368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.743644368
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.358754008
Short name T226
Test name
Test status
Simulation time 6450145916 ps
CPU time 89.38 seconds
Started May 14 01:09:57 PM PDT 24
Finished May 14 01:11:30 PM PDT 24
Peak memory 200600 kb
Host smart-a257f193-023c-469d-ae07-79d2b412a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358754008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.358754008
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2364715306
Short name T429
Test name
Test status
Simulation time 1864370734 ps
CPU time 5.07 seconds
Started May 14 01:09:39 PM PDT 24
Finished May 14 01:09:46 PM PDT 24
Peak memory 200652 kb
Host smart-5a522b8e-ce7f-4885-ab78-8dd223b470c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364715306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2364715306
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3710826867
Short name T449
Test name
Test status
Simulation time 179353993 ps
CPU time 1.02 seconds
Started May 14 01:10:01 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 199180 kb
Host smart-8a9b852e-cda6-485a-8b31-13697f4128e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710826867 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3710826867
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3449215148
Short name T428
Test name
Test status
Simulation time 176737095891 ps
CPU time 547.41 seconds
Started May 14 01:09:40 PM PDT 24
Finished May 14 01:18:49 PM PDT 24
Peak memory 200608 kb
Host smart-22d3b449-6406-402e-affb-b45adf9af473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449215148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3449215148
Directory /workspace/9.hmac_test_sha_vectors/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%