Summary for Variable digest_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
2 |
3 |
60.00 |
User Defined Bins for digest_size
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
sha2_invalid |
0 |
1 |
1 |
|
sha2_none |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sha2_512 |
1290 |
1 |
|
|
T3 |
8 |
|
T4 |
5 |
|
T5 |
1 |
sha2_384 |
1352 |
1 |
|
|
T3 |
5 |
|
T4 |
5 |
|
T5 |
3 |
sha2_256 |
13850 |
1 |
|
|
T1 |
4 |
|
T3 |
5 |
|
T4 |
3 |
Summary for Variable digest_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for digest_swap
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14529 |
1 |
|
|
T1 |
4 |
|
T3 |
8 |
|
T4 |
7 |
auto[1] |
1963 |
1 |
|
|
T3 |
10 |
|
T4 |
6 |
|
T5 |
7 |
Summary for Variable endian_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for endian_swap
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1913 |
1 |
|
|
T3 |
8 |
|
T4 |
6 |
|
T5 |
7 |
auto[1] |
14579 |
1 |
|
|
T1 |
4 |
|
T3 |
10 |
|
T4 |
7 |
Summary for Variable hmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for hmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
enabled |
2155 |
1 |
|
|
T1 |
4 |
|
T3 |
18 |
|
T4 |
13 |
disabled |
14337 |
1 |
|
|
T5 |
6 |
|
T6 |
194 |
|
T7 |
14 |
Summary for Variable key_length
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
7 |
1 |
6 |
85.71 |
User Defined Bins for key_length
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
key_invalid |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
key_none |
667 |
1 |
|
|
T5 |
3 |
|
T7 |
8 |
|
T14 |
6 |
key_1024 |
529 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
2 |
key_512 |
660 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
3 |
key_384 |
649 |
1 |
|
|
T3 |
6 |
|
T4 |
3 |
|
T5 |
3 |
key_256 |
13310 |
1 |
|
|
T1 |
4 |
|
T3 |
4 |
|
T4 |
1 |
key_128 |
677 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T5 |
1 |
Summary for Variable sha_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
1 |
1 |
50.00 |
User Defined Bins for sha_en
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
disabled |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
enabled |
16492 |
1 |
|
|
T1 |
4 |
|
T3 |
18 |
|
T4 |
13 |
Summary for Cross cfg_cross
Samples crossed: hmac_en endian_swap digest_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cfg_cross
Bins
hmac_en | endian_swap | digest_swap | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
enabled |
auto[0] |
auto[0] |
455 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
2 |
enabled |
auto[0] |
auto[1] |
453 |
1 |
|
|
T3 |
5 |
|
T4 |
2 |
|
T5 |
3 |
enabled |
auto[1] |
auto[0] |
727 |
1 |
|
|
T1 |
4 |
|
T3 |
5 |
|
T4 |
3 |
enabled |
auto[1] |
auto[1] |
520 |
1 |
|
|
T3 |
5 |
|
T4 |
4 |
|
T7 |
4 |
disabled |
auto[0] |
auto[0] |
499 |
1 |
|
|
T5 |
1 |
|
T7 |
2 |
|
T14 |
4 |
disabled |
auto[0] |
auto[1] |
506 |
1 |
|
|
T5 |
1 |
|
T7 |
8 |
|
T14 |
3 |
disabled |
auto[1] |
auto[0] |
12848 |
1 |
|
|
T5 |
1 |
|
T6 |
194 |
|
T9 |
194 |
disabled |
auto[1] |
auto[1] |
484 |
1 |
|
|
T5 |
3 |
|
T7 |
4 |
|
T14 |
2 |
Summary for Cross hmac_dis_x_sha_en
Samples crossed: hmac_en sha_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins |
3 |
2 |
1 |
33.33 |
2 |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for hmac_dis_x_sha_en
Element holes
hmac_en | sha_en | COUNT | AT LEAST | NUMBER | STATUS |
* |
[disabled] |
-- |
-- |
2 |
|
Covered bins
hmac_en | sha_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
enabled |
enabled |
2155 |
1 |
|
|
T1 |
4 |
|
T3 |
18 |
|
T4 |
13 |
User Defined Cross Bins for hmac_dis_x_sha_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
b0 |
14337 |
1 |
|
|
T5 |
6 |
|
T6 |
194 |
|
T7 |
14 |
Summary for Cross key_x_digest_mismatch
Samples crossed: key_length digest_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
35 |
17 |
18 |
51.43 |
17 |
Automatically Generated Cross Bins |
34 |
17 |
17 |
50.00 |
17 |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for key_x_digest_mismatch
Element holes
key_length | digest_size | COUNT | AT LEAST | NUMBER | STATUS |
[key_invalid] |
* |
-- |
-- |
5 |
|
Uncovered bins
key_length | digest_size | COUNT | AT LEAST | NUMBER | STATUS |
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128] |
[sha2_invalid , sha2_none] |
-- |
-- |
12 |
|
Covered bins
key_length | digest_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
key_none |
sha2_512 |
205 |
1 |
|
|
T7 |
5 |
|
T14 |
2 |
|
T15 |
1 |
key_none |
sha2_384 |
233 |
1 |
|
|
T14 |
2 |
|
T15 |
2 |
|
T17 |
1 |
key_none |
sha2_256 |
229 |
1 |
|
|
T5 |
3 |
|
T7 |
3 |
|
T14 |
2 |
key_1024 |
sha2_512 |
213 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
key_1024 |
sha2_384 |
230 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T14 |
2 |
key_512 |
sha2_512 |
224 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T7 |
2 |
key_512 |
sha2_384 |
224 |
1 |
|
|
T7 |
3 |
|
T14 |
1 |
|
T15 |
1 |
key_512 |
sha2_256 |
212 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
2 |
key_384 |
sha2_512 |
197 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T17 |
2 |
key_384 |
sha2_384 |
235 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
1 |
key_384 |
sha2_256 |
217 |
1 |
|
|
T3 |
2 |
|
T5 |
2 |
|
T7 |
1 |
key_256 |
sha2_512 |
228 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
2 |
key_256 |
sha2_384 |
207 |
1 |
|
|
T3 |
1 |
|
T32 |
1 |
|
T15 |
1 |
key_256 |
sha2_256 |
12875 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T5 |
1 |
key_128 |
sha2_512 |
223 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T7 |
1 |
key_128 |
sha2_384 |
223 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
2 |
key_128 |
sha2_256 |
231 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
2 |
User Defined Cross Bins for key_x_digest_mismatch
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
b0 |
86 |
1 |
|
|
T7 |
2 |
|
T28 |
1 |
|
T21 |
4 |
Summary for Cross key_length_x_digest_size
Samples crossed: key_length digest_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
17 |
18 |
51.43 |
17 |
Automatically Generated Cross Bins for key_length_x_digest_size
Element holes
key_length | digest_size | COUNT | AT LEAST | NUMBER | STATUS |
[key_invalid] |
* |
-- |
-- |
5 |
|
Uncovered bins
key_length | digest_size | COUNT | AT LEAST | NUMBER | STATUS |
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128] |
[sha2_invalid , sha2_none] |
-- |
-- |
12 |
|
Covered bins
key_length | digest_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
key_none |
sha2_512 |
205 |
1 |
|
|
T7 |
5 |
|
T14 |
2 |
|
T15 |
1 |
key_none |
sha2_384 |
233 |
1 |
|
|
T14 |
2 |
|
T15 |
2 |
|
T17 |
1 |
key_none |
sha2_256 |
229 |
1 |
|
|
T5 |
3 |
|
T7 |
3 |
|
T14 |
2 |
key_1024 |
sha2_512 |
213 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
key_1024 |
sha2_384 |
230 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T14 |
2 |
key_1024 |
sha2_256 |
86 |
1 |
|
|
T7 |
2 |
|
T28 |
1 |
|
T21 |
4 |
key_512 |
sha2_512 |
224 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T7 |
2 |
key_512 |
sha2_384 |
224 |
1 |
|
|
T7 |
3 |
|
T14 |
1 |
|
T15 |
1 |
key_512 |
sha2_256 |
212 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
2 |
key_384 |
sha2_512 |
197 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T17 |
2 |
key_384 |
sha2_384 |
235 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
1 |
key_384 |
sha2_256 |
217 |
1 |
|
|
T3 |
2 |
|
T5 |
2 |
|
T7 |
1 |
key_256 |
sha2_512 |
228 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
2 |
key_256 |
sha2_384 |
207 |
1 |
|
|
T3 |
1 |
|
T32 |
1 |
|
T15 |
1 |
key_256 |
sha2_256 |
12875 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T5 |
1 |
key_128 |
sha2_512 |
223 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T7 |
1 |
key_128 |
sha2_384 |
223 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
2 |
key_128 |
sha2_256 |
231 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
2 |