ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Category 0 | 384 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Severity 0 | 384 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 384 | 100.00 |
Uncovered | 2 | 0.52 |
Success | 378 | 98.44 |
Failure | 0 | 0.00 |
Incomplete | 3 | 0.78 |
Without Attempts | 0 | 0.00 |
Excluded | 4 | 1.04 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_tlul_adapter.rvalidHighReqFifoEmpty | 0 | 0 | 200993271 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.rvalidHighWhenRspFifoFull | 0 | 0 | 200993271 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_packer.DataIStable_M | 0 | 0 | 200993271 | 577468 | 0 | 439 | |
tb.dut.u_packer.DataOStableWhenPending_A | 0 | 0 | 200993271 | 657417 | 0 | 439 | |
tb.dut.u_packer.FlushFollowedByDone_A | 0 | 0 | 200993271 | 16492 | 0 | 439 |
ASSERTIONS | CATEGORY | SEVERITY | EXCLUSION | EXCLUDE ANNOTATION | SRC |
tb.dut.u_tlul_adapter.u_rspfifo.DataKnown_A | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_sramreqfifo.DataKnown_A | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv | |
tb.dut.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | Excluded | [UNSUPPORTED] excluded by fpv |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 223719584 | 159748 | 159748 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 223719584 | 615 | 615 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 223719584 | 627 | 627 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 223719584 | 355 | 355 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 223719584 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 223719584 | 279 | 279 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 223719584 | 268 | 268 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 223719584 | 13622 | 13622 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 223719584 | 2063850 | 2063850 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 223719584 | 19430033 | 19430033 | 582 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 223719584 | 159748 | 159748 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 223719584 | 615 | 615 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 223719584 | 627 | 627 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 223719584 | 355 | 355 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 223719584 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 223719584 | 279 | 279 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 223719584 | 268 | 268 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 223719584 | 13622 | 13622 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 223719584 | 2063850 | 2063850 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 223719584 | 19430033 | 19430033 | 582 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |