Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14270545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15379009

1

T1

793

T2

15936

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11624647	1			T1	691		T2	1429		T3	1
values[0x0]	8421037	1			T1	457		T2	8295		T3	6
values[0x1]	9603870	1			T1	564		T2	8868		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10597269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19052285

1

T1

1038

T2

16945

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	98798	1			T1	5		T2	71		T4	133
valid_sources[0x01]	101933	1			T1	15		T2	66		T4	139
valid_sources[0x02]	100180	1			T1	3		T2	56		T4	133
valid_sources[0x03]	104898	1			T1	1		T2	69		T4	120
valid_sources[0x04]	137085	1			T1	2		T2	64		T4	119
valid_sources[0x05]	126854	1			T1	6		T2	71		T4	137
valid_sources[0x06]	104327	1			T1	14		T2	84		T4	151
valid_sources[0x07]	119306	1			T1	6		T2	70		T4	131
valid_sources[0x08]	100254	1			T1	4		T2	88		T4	132
valid_sources[0x09]	127442	1			T1	21		T2	72		T3	1
valid_sources[0x0a]	125988	1			T1	16		T2	56		T4	121
valid_sources[0x0b]	132601	1			T1	5		T2	76		T4	133
valid_sources[0x0c]	106509	1			T1	9		T2	69		T4	136
valid_sources[0x0d]	143594	1			T1	3		T2	56		T4	120
valid_sources[0x0e]	102392	1			T1	20		T2	78		T4	125
valid_sources[0x0f]	107342	1			T2	77		T4	118		T7	4332
valid_sources[0x10]	255973	1			T1	12		T2	66		T4	152
valid_sources[0x11]	102048	1			T2	65		T4	116		T7	2136
valid_sources[0x12]	102176	1			T1	10		T2	58		T4	137
valid_sources[0x13]	106126	1			T1	10		T2	68		T4	111
valid_sources[0x14]	106496	1			T1	18		T2	64		T4	106
valid_sources[0x15]	117643	1			T1	2		T2	78		T4	118
valid_sources[0x16]	124815	1			T1	3		T2	80		T4	122
valid_sources[0x17]	127171	1			T1	6		T2	65		T4	120
valid_sources[0x18]	106489	1			T1	8		T2	73		T3	2
valid_sources[0x19]	105118	1			T1	2		T2	92		T3	1
valid_sources[0x1a]	147117	1			T1	3		T2	64		T4	99
valid_sources[0x1b]	108552	1			T1	4		T2	80		T4	131
valid_sources[0x1c]	106790	1			T1	3		T2	69		T3	1
valid_sources[0x1d]	101908	1			T1	4		T2	95		T4	120
valid_sources[0x1e]	109871	1			T1	6		T2	63		T4	153
valid_sources[0x1f]	106955	1			T1	9		T2	87		T4	123
valid_sources[0x20]	107252	1			T1	12		T2	112		T4	139
valid_sources[0x21]	114970	1			T1	12		T2	82		T4	116
valid_sources[0x22]	101041	1			T1	5		T2	74		T4	128
valid_sources[0x23]	100214	1			T1	17		T2	62		T4	136
valid_sources[0x24]	100353	1			T1	7		T2	68		T4	129
valid_sources[0x25]	102347	1			T1	11		T2	81		T4	123
valid_sources[0x26]	111003	1			T1	7		T2	56		T4	130
valid_sources[0x27]	104101	1			T1	2		T2	88		T4	133
valid_sources[0x28]	177441	1			T1	6		T2	62		T4	116
valid_sources[0x29]	120432	1			T1	2		T2	80		T4	140
valid_sources[0x2a]	99648	1			T1	8		T2	84		T4	135
valid_sources[0x2b]	111444	1			T2	63		T4	124		T7	96
valid_sources[0x2c]	109620	1			T2	67		T4	114		T7	156
valid_sources[0x2d]	101162	1			T1	2		T2	54		T4	128
valid_sources[0x2e]	100604	1			T1	6		T2	73		T4	125
valid_sources[0x2f]	102856	1			T1	1		T2	51		T4	122
valid_sources[0x30]	100833	1			T1	1		T2	88		T4	121
valid_sources[0x31]	102612	1			T1	12		T2	90		T4	116
valid_sources[0x32]	109940	1			T1	3		T2	78		T4	116
valid_sources[0x33]	120641	1			T1	3		T2	60		T4	152
valid_sources[0x34]	112223	1			T2	94		T4	137		T7	101
valid_sources[0x35]	137748	1			T1	3		T2	62		T4	116
valid_sources[0x36]	152690	1			T1	11		T2	68		T4	131
valid_sources[0x37]	100288	1			T1	2		T2	62		T4	148
valid_sources[0x38]	122744	1			T1	9		T2	73		T4	111
valid_sources[0x39]	100523	1			T1	6		T2	69		T4	108
valid_sources[0x3a]	110069	1			T1	7		T2	93		T4	128
valid_sources[0x3b]	113898	1			T1	12		T2	66		T4	133
valid_sources[0x3c]	113232	1			T1	6		T2	65		T4	116
valid_sources[0x3d]	150127	1			T1	19		T2	57		T4	139
valid_sources[0x3e]	100000	1			T2	80		T4	117		T7	49
valid_sources[0x3f]	113766	1			T1	5		T2	95		T4	135
valid_sources[0x40]	101969	1			T1	12		T2	86		T4	131
valid_sources[0x41]	113709	1			T1	13		T2	88		T4	116
valid_sources[0x42]	121391	1			T2	68		T4	125		T7	119
valid_sources[0x43]	98697	1			T1	8		T2	62		T4	137
valid_sources[0x44]	151799	1			T2	86		T3	1		T4	129
valid_sources[0x45]	103645	1			T2	76		T4	121		T7	105
valid_sources[0x46]	175864	1			T2	56		T4	124		T7	48
valid_sources[0x47]	105652	1			T1	11		T2	91		T4	134
valid_sources[0x48]	160937	1			T1	26		T2	55		T3	1
valid_sources[0x49]	108323	1			T1	8		T2	66		T3	1
valid_sources[0x4a]	111251	1			T1	16		T2	59		T3	1
valid_sources[0x4b]	121174	1			T1	6		T2	81		T4	125
valid_sources[0x4c]	98894	1			T1	9		T2	53		T4	152
valid_sources[0x4d]	101420	1			T1	20		T2	85		T4	136
valid_sources[0x4e]	101291	1			T1	12		T2	74		T4	123
valid_sources[0x4f]	100365	1			T1	1		T2	59		T4	112
valid_sources[0x50]	98375	1			T1	7		T2	65		T4	134
valid_sources[0x51]	119706	1			T2	56		T3	1		T4	148
valid_sources[0x52]	108309	1			T2	83		T4	144		T7	40
valid_sources[0x53]	99967	1			T1	4		T2	65		T4	131
valid_sources[0x54]	115112	1			T1	8		T2	73		T4	109
valid_sources[0x55]	103112	1			T2	83		T4	128		T7	175
valid_sources[0x56]	103779	1			T1	5		T2	71		T4	131
valid_sources[0x57]	108819	1			T1	11		T2	64		T4	136
valid_sources[0x58]	115623	1			T1	4		T2	59		T4	110
valid_sources[0x59]	107146	1			T1	2		T2	80		T4	119
valid_sources[0x5a]	101492	1			T2	53		T4	121		T7	45
valid_sources[0x5b]	127364	1			T1	5		T2	81		T4	132
valid_sources[0x5c]	100726	1			T2	74		T4	107		T7	113
valid_sources[0x5d]	116320	1			T1	1		T2	67		T4	130
valid_sources[0x5e]	104114	1			T1	4		T2	71		T4	113
valid_sources[0x5f]	101703	1			T1	5		T2	65		T4	112
valid_sources[0x60]	105192	1			T1	1		T2	79		T4	112
valid_sources[0x61]	99120	1			T1	9		T2	85		T4	130
valid_sources[0x62]	108106	1			T2	58		T4	140		T7	81
valid_sources[0x63]	109777	1			T1	5		T2	69		T4	118
valid_sources[0x64]	105115	1			T1	6		T2	63		T4	139
valid_sources[0x65]	125781	1			T1	18		T2	67		T4	118
valid_sources[0x66]	100504	1			T1	5		T2	70		T4	140
valid_sources[0x67]	124037	1			T1	8		T2	76		T4	118
valid_sources[0x68]	140780	1			T1	4		T2	77		T4	118
valid_sources[0x69]	105648	1			T1	3		T2	63		T4	165
valid_sources[0x6a]	107833	1			T1	6		T2	63		T4	118
valid_sources[0x6b]	129860	1			T1	3		T2	78		T4	141
valid_sources[0x6c]	101079	1			T1	3		T2	86		T4	116
valid_sources[0x6d]	102023	1			T1	9		T2	66		T4	154
valid_sources[0x6e]	151098	1			T1	2		T2	72		T4	131
valid_sources[0x6f]	98200	1			T1	5		T2	74		T4	122
valid_sources[0x70]	119420	1			T2	63		T4	130		T7	131
valid_sources[0x71]	104646	1			T1	9		T2	76		T4	126
valid_sources[0x72]	136406	1			T1	8		T2	81		T4	149
valid_sources[0x73]	106567	1			T1	2		T2	65		T4	138
valid_sources[0x74]	162297	1			T2	64		T4	114		T7	90
valid_sources[0x75]	138664	1			T1	11		T2	70		T4	110
valid_sources[0x76]	139084	1			T1	21		T2	84		T4	125
valid_sources[0x77]	103067	1			T1	8		T2	82		T3	2
valid_sources[0x78]	104195	1			T1	5		T2	68		T4	131
valid_sources[0x79]	99073	1			T1	4		T2	69		T4	119
valid_sources[0x7a]	107104	1			T1	1		T2	64		T4	139
valid_sources[0x7b]	110724	1			T1	2		T2	95		T4	135
valid_sources[0x7c]	101036	1			T2	84		T4	130		T7	116
valid_sources[0x7d]	106687	1			T1	3		T2	78		T4	127
valid_sources[0x7e]	101410	1			T1	20		T2	58		T4	137
valid_sources[0x7f]	177685	1			T1	1		T2	75		T4	115
valid_sources[0x80]	99980	1			T1	2		T2	68		T4	131

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5735477

1

T1

336

T2

496

T4

1094

values[0x0]

all_enables

biggest_size

5086976

1

T1

226

T2

7704

T3

3

values[0x1]

all_enables

biggest_size

4556556

1

T1

231

T2

7736

T3

1