Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14945965

1

T1

919

T2

2656

T3

14

full_word

15422981

1

T1

793

T2

15936

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30368606	1			T1	1712		T2	18592		T3	18
auto[TlIntgErrCmd]	119	1			T56	6		T57	5		T58	4
auto[TlIntgErrData]	116	1			T56	12		T57	3		T58	4
auto[TlIntgErrBoth]	105	1			T56	2		T57	2		T58	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11852050

1

T1

691

T2

1429

T3

1

auto[1]

18516896

1

T1

1021

T2

17163

T3

17

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6099162	1			T1	355		T2	933		T3	1
auto[TlIntgErrNone]	partial	auto[1]	8846491	1			T1	564		T2	1723		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	5752737	1			T1	336		T2	496		T4	1094
auto[TlIntgErrNone]	full_word	auto[1]	9670216	1			T1	457		T2	15440		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T56	1		T57	2		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T56	5		T57	3		T58	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T116	1		T117	1		T118	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T115	1		T118	2		T119	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T56	6		T57	1		T58	1
auto[TlIntgErrData]	partial	auto[1]	58	1			T56	5		T57	2		T58	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T56	1		T111	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T111	1		T121	2		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T58	6		T111	2		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T56	2		T57	1		T58	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T57	1		T122	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T120	1		T116	1		T115	1