Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16778016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17966656

1

T1

131

T2

2028

T3

15338

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13656070	1			T1	127		T2	1517		T3	13474
values[0x0]	9820885	1			T1	60		T2	781		T3	8840
values[0x1]	11267717	1			T1	69		T2	894		T3	11114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12430957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22313715

1

T1

167

T2

2313

T3

20178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	114437	1			T2	20		T3	104		T9	1
valid_sources[0x01]	140221	1			T3	113		T9	1		T10	23
valid_sources[0x02]	174425	1			T3	151		T4	2		T10	8
valid_sources[0x03]	137569	1			T1	2		T2	4		T3	129
valid_sources[0x04]	178778	1			T1	11		T3	140		T9	1
valid_sources[0x05]	117984	1			T3	162		T4	33		T10	12
valid_sources[0x06]	143540	1			T3	158		T4	8		T10	11
valid_sources[0x07]	126568	1			T1	1		T3	127		T4	5
valid_sources[0x08]	180733	1			T3	120		T10	1		T6	65
valid_sources[0x09]	147180	1			T2	1		T3	129		T9	1
valid_sources[0x0a]	112750	1			T3	103		T10	3		T6	103
valid_sources[0x0b]	109553	1			T3	131		T10	2		T6	65
valid_sources[0x0c]	216854	1			T2	15		T3	148		T4	5
valid_sources[0x0d]	154223	1			T2	8		T3	116		T9	3
valid_sources[0x0e]	126448	1			T2	57		T3	140		T9	1
valid_sources[0x0f]	124897	1			T3	96		T9	2		T10	23
valid_sources[0x10]	185771	1			T2	3		T3	149		T9	1
valid_sources[0x11]	130737	1			T2	25		T3	111		T9	2
valid_sources[0x12]	115074	1			T3	119		T10	8		T6	6
valid_sources[0x13]	121314	1			T3	157		T4	1		T10	11
valid_sources[0x14]	135459	1			T3	154		T10	8		T6	34
valid_sources[0x15]	111931	1			T3	134		T9	1		T10	7
valid_sources[0x16]	115525	1			T1	4		T2	12		T3	124
valid_sources[0x17]	129510	1			T1	2		T3	168		T10	10
valid_sources[0x18]	187097	1			T3	139		T4	5		T10	3
valid_sources[0x19]	154381	1			T3	133		T4	28		T10	17
valid_sources[0x1a]	110638	1			T3	136		T9	1		T4	11
valid_sources[0x1b]	108424	1			T3	127		T4	1		T10	14
valid_sources[0x1c]	174250	1			T1	1		T3	128		T9	1
valid_sources[0x1d]	125215	1			T1	3		T2	23		T3	139
valid_sources[0x1e]	128989	1			T3	142		T4	10		T10	5
valid_sources[0x1f]	116814	1			T1	5		T3	117		T9	1
valid_sources[0x20]	117761	1			T1	3		T3	128		T10	9
valid_sources[0x21]	122356	1			T2	110		T3	99		T10	5
valid_sources[0x22]	128152	1			T1	1		T2	11		T3	100
valid_sources[0x23]	109190	1			T2	5		T3	102		T4	4
valid_sources[0x24]	162817	1			T3	117		T4	1		T10	17
valid_sources[0x25]	137201	1			T3	140		T4	1		T10	4
valid_sources[0x26]	126180	1			T1	3		T3	129		T9	1
valid_sources[0x27]	133000	1			T1	1		T2	85		T3	107
valid_sources[0x28]	117308	1			T3	110		T9	1		T4	4
valid_sources[0x29]	135610	1			T1	2		T3	116		T4	9
valid_sources[0x2a]	135295	1			T1	4		T3	134		T10	11
valid_sources[0x2b]	161138	1			T2	117		T3	115		T4	3
valid_sources[0x2c]	118808	1			T3	113		T9	1		T10	8
valid_sources[0x2d]	148390	1			T1	3		T3	147		T9	2
valid_sources[0x2e]	118502	1			T1	5		T3	130		T4	4
valid_sources[0x2f]	138620	1			T3	143		T10	11		T6	75
valid_sources[0x30]	157034	1			T3	118		T9	2		T4	9
valid_sources[0x31]	128538	1			T1	1		T3	114		T9	1
valid_sources[0x32]	152366	1			T3	133		T9	1		T10	5
valid_sources[0x33]	111450	1			T1	1		T3	133		T4	14
valid_sources[0x34]	129256	1			T3	175		T9	2		T10	6
valid_sources[0x35]	109116	1			T3	132		T10	9		T6	13
valid_sources[0x36]	121793	1			T1	3		T2	13		T3	168
valid_sources[0x37]	139174	1			T3	135		T10	20		T6	109
valid_sources[0x38]	111533	1			T1	1		T2	15		T3	101
valid_sources[0x39]	121307	1			T3	137		T9	3		T10	15
valid_sources[0x3a]	135079	1			T3	108		T4	8		T10	19
valid_sources[0x3b]	119973	1			T3	136		T10	9		T6	53
valid_sources[0x3c]	163350	1			T3	135		T10	20		T6	94
valid_sources[0x3d]	185579	1			T2	9		T3	174		T4	24
valid_sources[0x3e]	110078	1			T1	4		T2	6		T3	130
valid_sources[0x3f]	133185	1			T3	132		T9	2		T4	9
valid_sources[0x40]	112611	1			T3	129		T4	9		T10	14
valid_sources[0x41]	233403	1			T1	5		T3	106		T9	2
valid_sources[0x42]	123550	1			T3	111		T4	30		T10	5
valid_sources[0x43]	113455	1			T1	1		T3	143		T10	11
valid_sources[0x44]	126199	1			T1	7		T2	4		T3	135
valid_sources[0x45]	111758	1			T3	152		T10	6		T6	19
valid_sources[0x46]	125940	1			T3	122		T9	2		T10	13
valid_sources[0x47]	194097	1			T1	1		T3	170		T10	12
valid_sources[0x48]	110326	1			T2	1		T3	154		T9	2
valid_sources[0x49]	109272	1			T3	152		T4	2		T10	12
valid_sources[0x4a]	131924	1			T1	1		T2	44		T3	112
valid_sources[0x4b]	114428	1			T3	148		T10	10		T6	18
valid_sources[0x4c]	124213	1			T3	109		T4	6		T10	8
valid_sources[0x4d]	150520	1			T3	137		T4	5		T10	7
valid_sources[0x4e]	109294	1			T1	3		T2	68		T3	106
valid_sources[0x4f]	128715	1			T1	7		T3	127		T4	1
valid_sources[0x50]	157723	1			T1	2		T3	133		T9	3
valid_sources[0x51]	143966	1			T3	181		T4	34		T10	31
valid_sources[0x52]	126030	1			T1	8		T3	125		T4	37
valid_sources[0x53]	165678	1			T3	133		T9	1		T4	9
valid_sources[0x54]	259640	1			T3	133		T9	3		T4	9
valid_sources[0x55]	112694	1			T3	110		T10	4		T6	44
valid_sources[0x56]	116778	1			T1	1		T2	57		T3	129
valid_sources[0x57]	127964	1			T1	1		T3	147		T9	1
valid_sources[0x58]	137421	1			T1	1		T2	120		T3	135
valid_sources[0x59]	127912	1			T1	1		T3	118		T4	9
valid_sources[0x5a]	114050	1			T3	126		T9	2		T10	5
valid_sources[0x5b]	135003	1			T2	48		T3	123		T10	2
valid_sources[0x5c]	142212	1			T1	2		T3	109		T9	1
valid_sources[0x5d]	126647	1			T3	125		T4	2		T10	9
valid_sources[0x5e]	150989	1			T2	24		T3	160		T4	22
valid_sources[0x5f]	129577	1			T1	2		T2	3		T3	139
valid_sources[0x60]	140148	1			T3	162		T10	19		T6	141
valid_sources[0x61]	112987	1			T3	118		T9	1		T10	8
valid_sources[0x62]	151245	1			T3	161		T10	15		T6	31
valid_sources[0x63]	161761	1			T2	29		T3	129		T10	3
valid_sources[0x64]	112112	1			T3	134		T10	2		T6	136
valid_sources[0x65]	180381	1			T1	5		T3	110		T10	9
valid_sources[0x66]	196806	1			T1	1		T2	81		T3	93
valid_sources[0x67]	183892	1			T1	1		T2	14		T3	162
valid_sources[0x68]	122006	1			T2	17		T3	126		T10	11
valid_sources[0x69]	150221	1			T1	4		T2	5		T3	161
valid_sources[0x6a]	164917	1			T1	4		T3	129		T9	1
valid_sources[0x6b]	125169	1			T2	49		T3	112		T10	2
valid_sources[0x6c]	148805	1			T2	15		T3	116		T4	13
valid_sources[0x6d]	148814	1			T3	138		T9	1		T10	10
valid_sources[0x6e]	150677	1			T3	152		T10	7		T6	77
valid_sources[0x6f]	115164	1			T3	152		T4	6		T10	1
valid_sources[0x70]	113377	1			T3	113		T9	4		T4	9
valid_sources[0x71]	113702	1			T3	134		T4	14		T10	10
valid_sources[0x72]	121710	1			T3	109		T9	1		T10	16
valid_sources[0x73]	165136	1			T3	107		T9	1		T10	23
valid_sources[0x74]	123829	1			T2	63		T3	144		T9	4
valid_sources[0x75]	132287	1			T1	1		T2	184		T3	141
valid_sources[0x76]	141770	1			T3	125		T9	1		T4	7
valid_sources[0x77]	112208	1			T3	95		T9	1		T4	7
valid_sources[0x78]	161106	1			T3	121		T9	1		T21	1
valid_sources[0x79]	111604	1			T1	5		T3	150		T9	1
valid_sources[0x7a]	111728	1			T2	87		T3	156		T10	12
valid_sources[0x7b]	249387	1			T1	3		T3	119		T9	1
valid_sources[0x7c]	114122	1			T2	10		T3	149		T9	5
valid_sources[0x7d]	117384	1			T3	108		T10	8		T6	47
valid_sources[0x7e]	134319	1			T3	132		T10	16		T6	81
valid_sources[0x7f]	183427	1			T2	13		T3	129		T9	2
valid_sources[0x80]	173731	1			T3	113		T9	1		T10	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6759567

1

T1

67

T2

741

T3

6760

values[0x0]

all_enables

biggest_size

5908082

1

T1

37

T2

625

T3

4556

values[0x1]

all_enables

biggest_size

5299007

1

T1

27

T2

662

T3

4022