Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

18287770

1

T1

125

T2

1164

T3

18090

full_word

18065222

1

T1

131

T2

2028

T3

15338

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36352582	1			T1	256		T2	3192		T3	33428
auto[TlIntgErrCmd]	138	1			T52	4		T53	5		T54	7
auto[TlIntgErrData]	133	1			T52	4		T53	2		T54	5
auto[TlIntgErrBoth]	139	1			T52	2		T53	3		T54	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14170342

1

T1

127

T2

1517

T3

13474

auto[1]

22182650

1

T1

129

T2

1675

T3

19954

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7371272	1			T1	60		T2	776		T3	6714
auto[TlIntgErrNone]	partial	auto[1]	10916127	1			T1	65		T2	388		T3	11376
auto[TlIntgErrNone]	full_word	auto[0]	6798879	1			T1	67		T2	741		T3	6760
auto[TlIntgErrNone]	full_word	auto[1]	11266304	1			T1	64		T2	1287		T3	8578
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T52	2		T53	3		T54	4
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T52	1		T53	2		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T111	1		T59	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T52	1		T112	2		T113	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T52	3		T54	2		T110	8
auto[TlIntgErrData]	partial	auto[1]	48	1			T54	3		T110	3		T111	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T53	1		T112	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T52	1		T53	1		T114	2
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T53	1		T54	3		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T52	2		T53	2		T54	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T59	1		T113	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	2		T116	1		T117	1