Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.64	95.29	83.54	100.00	40.00	89.01	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	210616462	863570	0	0
intr_enable_rd_A	210616462	2913	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210616462	863570	0	0
T15	210377	91861	0	0
T29	0	67167	0	0
T30	0	212309	0	0
T52	0	3	0	0
T53	0	3	0	0
T61	0	8	0	0
T62	0	754	0	0
T63	0	280	0	0
T64	0	684	0	0
T65	0	1234	0	0
T66	791736	0	0	0
T67	258038	0	0	0
T68	250385	0	0	0
T69	359225	0	0	0
T70	5400	0	0	0
T71	1031	0	0	0
T72	47206	0	0	0
T73	1212	0	0	0
T74	4067	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210616462	2913	0	0
T52	9019	39	0	0
T53	9801	34	0	0
T61	3835	15	0	0
T64	14948	2	0	0
T75	4215	1	0	0
T76	1255	18	0	0
T77	1656	17	0	0
T78	1793	12	0	0
T79	53191	198	0	0
T80	15058	29	0	0