Module Definition
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Module : hmac_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.00 95.33 92.05 100.00 88.61

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_hmac 94.00 95.33 92.05 100.00 88.61



Module Instance : tb.dut.u_hmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.00 95.33 92.05 100.00 88.61


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.00 95.33 92.05 100.00 88.61


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.64 95.29 83.54 100.00 40.00 89.01 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : hmac_core
Line No.TotalCoveredPercent
TOTAL15014395.33
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
ALWAYS1322121100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19111100.00
ALWAYS207161593.75
CONT_ASSIGN23111100.00
ALWAYS23444100.00
CONT_ASSIGN24211100.00
ALWAYS25010660.00
ALWAYS26833100.00
ALWAYS27466100.00
ALWAYS28444100.00
ALWAYS29266100.00
CONT_ASSIGN30111100.00
ALWAYS30433100.00
ALWAYS309646296.88
CONT_ASSIGN43811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
121 1 1
122 1 1
124 1 1
125 1 1
127 1 1
128 1 1
132 1 1
134 1 1
136 1 1
138 1 1
140 1 1
144 1 1
146 1 1
148 1 1
150 1 1
154 1 1
156 1 1
158 1 1
160 1 1
164 1 1
165 1 1
167 1 1
168 1 1
173 1 1
174 1 1
176 1 1
177 1 1
188 1 1
190 1 1
191 1 1
207 1 1
208 1 1
209 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
MISSING_ELSE
218 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
MISSING_ELSE
228 0 1
231 1 1
234 1 1
235 1 1
236 1 1
237 1 1
242 1 1
250 1 1
251 1 1
252 1 1
253 1 1
256 0 1
257 0 1
258 0 1
259 0 1
262 1 1
263 1 1
MISSING_ELSE
268 2 2
269 1 1
274 1 1
275 1 1
276 1 1
277 1 1
278 1 1
279 1 1
MISSING_ELSE
284 1 1
285 1 1
286 1 1
287 1 1
MISSING_ELSE
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
==> MISSING_ELSE
301 1 1
304 2 2
305 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
323 1 1
325 1 1
326 1 1
328 1 1
329 1 1
330 1 1
331 1 1
333 1 1
338 1 1
340 1 1
341 1 1
343 1 1
345 1 1
347 1 1
352 1 1
353 1 1
355 1 1
356 0 1
357 0 1
MISSING_ELSE
360 1 1
362 1 1
363 1 1
364 1 1
366 1 1
367 1 1
372 1 1
374 1 1
375 1 1
376 1 1
378 1 1
381 1 1
386 1 1
387 1 1
388 1 1
389 1 1
391 1 1
395 1 1
397 1 1
398 1 1
399 1 1
400 1 1
402 1 1
408 1 1
409 1 1
411 1 1
412 1 1
414 1 1
416 1 1
418 1 1
424 1 1
426 1 1
438 1 1


Cond Coverage for Module : hmac_core
TotalCoveredPercent
Conditions17616292.05
Logical17616292.05
Non-Logical00
Event00

 LINE       121
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       122
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       124
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       124
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       188
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       188
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       188
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       190
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       191
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T9,T10

 LINE       191
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T9,T10

 LINE       191
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10Not Covered
11CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T5
10CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T9,T10

 LINE       191
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T9,T10

 LINE       191
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10Not Covered
11CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T5
10CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       191
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       191
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       212
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T9

 LINE       215
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------
-1--2-StatusTests
00CoveredT2,T5,T10
01CoveredT2,T3,T5
10CoveredT2,T3,T5

 LINE       215
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       215
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       218
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       220
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

 LINE       222
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT2,T3,T5

 LINE       224
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT2,T3,T10

 LINE       235
 EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       237
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       242
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       278
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       296
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       301
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       325
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       353
 EXPRESSION (round_q == Outer)
            ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       355
 EXPRESSION ((round_q == Inner) && reg_hash_continue_i)
             ---------1--------    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       355
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       360
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T3,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       360
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       360
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       360
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       360
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 EXPRESSION (round_q == Outer)
            ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       375
 EXPRESSION (round_q == Outer)
            ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T5
010CoveredT2,T3,T10
100CoveredT1,T9,T10

 LINE       391
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T9,T10
10CoveredT2,T3,T5
11CoveredT1,T9,T10

 LINE       391
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T9,T10

 LINE       391
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T10
10Not Covered
11CoveredT2,T3,T10

 LINE       391
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10

 LINE       391
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10

 LINE       391
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T10
11CoveredT2,T3,T5

 LINE       391
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       391
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       438
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start_i || reg_hash_continue_i) ))
             --------1-------    -----------------------2-----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       438
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       438
 SUB-EXPRESSION ( ! (reg_hash_start_i || reg_hash_continue_i) )
                    --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       438
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

FSM Coverage for Module : hmac_core
Summary for FSM :: st_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StDone 376 Covered T1,T2,T3
StIPad 326 Covered T1,T2,T3
StIdle 333 Covered T1,T2,T3
StMsg 341 Covered T1,T2,T3
StOPad 395 Covered T1,T2,T3
StPushToMsgFifo 378 Covered T1,T2,T3
StWaitResp 362 Covered T1,T2,T3


transitionsLine No.CoveredTests
StDone->StIdle 424 Covered T1,T2,T3
StIPad->StMsg 341 Covered T1,T2,T3
StIdle->StIPad 326 Covered T1,T2,T3
StMsg->StWaitResp 362 Covered T1,T2,T3
StOPad->StMsg 412 Covered T1,T2,T3
StPushToMsgFifo->StOPad 395 Covered T1,T2,T3
StWaitResp->StDone 376 Covered T1,T2,T3
StWaitResp->StPushToMsgFifo 378 Covered T1,T2,T3



Branch Coverage for Module : hmac_core
Line No.TotalCoveredPercent
Branches 79 70 88.61
TERNARY 121 2 2 100.00
TERNARY 122 2 2 100.00
TERNARY 124 2 2 100.00
TERNARY 125 2 2 100.00
TERNARY 188 2 2 100.00
TERNARY 190 2 2 100.00
TERNARY 191 7 6 85.71
TERNARY 301 2 2 100.00
CASE 132 6 6 100.00
IF 208 9 8 88.89
CASE 234 4 4 100.00
IF 251 7 3 42.86
IF 268 2 2 100.00
IF 274 4 4 100.00
IF 284 3 3 100.00
IF 292 4 3 75.00
IF 304 2 2 100.00
CASE 323 17 15 88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 121 (hmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 (hmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 (hmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 125 (hmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 188 (hmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 190 ((!hmac_en_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 ((!hmac_en_i)) ? -2-: 191 (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? -3-: 191 (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? -4-: 191 (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? -5-: 191 (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? -6-: 191 ((sel_rdata == SelFifo)) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T9,T10
0 0 1 - - - Covered T2,T3,T5
0 0 0 1 - - Covered T1,T9,T10
0 0 0 0 1 - Covered T2,T3,T5
0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 Not Covered


LineNo. Expression -1-: 301 ((round_q == Inner)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 132 case (key_length_i)

Branches:
-1-StatusTests
Key_128 Covered T2,T3,T5
Key_256 Covered T1,T2,T3
Key_384 Covered T2,T3,T5
Key_512 Covered T2,T3,T10
Key_1024 Covered T2,T3,T10
default Covered T1,T2,T3


LineNo. Expression -1-: 208 if ((!hmac_en_i)) -2-: 212 if ((sel_msglen == SelIPadMsg)) -3-: 213 if ((digest_size_i == SHA2_256)) -4-: 215 if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) -5-: 218 if ((sel_msglen == SelOPadMsg)) -6-: 220 if ((digest_size_i == SHA2_256)) -7-: 222 if ((digest_size_i == SHA2_384)) -8-: 224 if ((digest_size_i == SHA2_512))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
1 - - - - - - - Covered T1,T2,T3
0 1 1 - - - - - Covered T1,T2,T9
0 1 0 1 - - - - Covered T2,T3,T5
0 1 0 0 - - - - Covered T2,T5,T10
0 0 - - 1 1 - - Covered T1,T2,T3
0 0 - - 1 0 1 - Covered T2,T3,T5
0 0 - - 1 0 0 1 Covered T2,T3,T10
0 0 - - 1 0 0 0 Covered T2,T3,T10
0 0 - - 0 - - - Not Covered


LineNo. Expression -1-: 234 case (digest_size_i)

Branches:
-1-StatusTests
SHA2_256 Covered T1,T2,T3
SHA2_384 Covered T2,T3,T5
SHA2_512 Covered T2,T3,T4
default Covered T1,T2,T3


LineNo. Expression -1-: 251 if (clr_txcount) -2-: 253 if (load_txcount) -3-: 256 case (digest_size_i) -4-: 262 if (inc_txcount)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 SHA2_256 - Not Covered
0 1 SHA2_384 - Not Covered
0 1 SHA2_512 - Not Covered
0 1 default - Not Covered
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 274 if ((!rst_ni)) -2-: 276 if (reg_hash_process_i) -3-: 278 if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 284 if ((!rst_ni)) -2-: 286 if (update_round)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 292 if ((!rst_ni)) -2-: 294 if (clr_fifo_wdata_sel) -3-: 296 if ((fifo_wsel_o && fifo_wvalid_o))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 304 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 323 case (st_q) -2-: 325 if ((hmac_en_i && reg_hash_start_i)) -3-: 340 if (txcnt_eq_blksz) -4-: 355 if (((round_q == Inner) && reg_hash_continue_i)) -5-: 360 if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))) -6-: 374 if (sha_hash_done_i) -7-: 375 if ((round_q == Outer)) -8-: 391 if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))) -9-: 411 if (txcnt_eq_blksz)

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
StIdle 1 - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - Covered T1,T2,T3
StIPad - 1 - - - - - - Covered T1,T2,T3
StIPad - 0 - - - - - - Covered T1,T2,T3
StMsg - - 1 - - - - - Not Covered
StMsg - - 0 - - - - - Covered T1,T2,T3
StMsg - - - 1 - - - - Covered T1,T2,T3
StMsg - - - 0 - - - - Covered T1,T2,T3
StWaitResp - - - - 1 1 - - Covered T1,T2,T3
StWaitResp - - - - 1 0 - - Covered T1,T2,T3
StWaitResp - - - - 0 - - - Covered T1,T2,T3
StPushToMsgFifo - - - - - - 1 - Covered T1,T2,T3
StPushToMsgFifo - - - - - - 0 - Covered T1,T2,T3
StOPad - - - - - - - 1 Covered T1,T2,T3
StOPad - - - - - - - 0 Covered T1,T2,T3
StDone - - - - - - - - Covered T1,T2,T3
default - - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%