Module Definition
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Module : prim_sha2_32
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.33 100.00 94.37 97.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_sha2_512 97.33 100.00 94.37 97.62



Module Instance : tb.dut.u_prim_sha2_512

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.33 100.00 94.37 97.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.61 97.00 92.96 60.00 88.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.64 95.29 83.54 100.00 40.00 89.01 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_multimode_logic.u_prim_sha2_multimode 83.59 95.88 92.59 60.00 85.91


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sha2_32
Line No.TotalCoveredPercent
TOTAL100100100.00
CONT_ASSIGN4211100.00
ALWAYS618787100.00
ALWAYS21033100.00
ALWAYS21533100.00
ALWAYS22033100.00
ALWAYS22533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
70 2 2
71 1 1
73 1 1
74 1 1
75 1 1
77 1 1
78 1 1
79 1 1
80 1 1
82 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
MISSING_ELSE
92 1 1
94 1 1
96 1 1
99 1 1
100 1 1
102 1 1
103 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
112 1 1
113 1 1
MISSING_ELSE
115 1 1
117 1 1
118 1 1
119 1 1
121 1 1
122 1 1
124 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
MISSING_ELSE
132 1 1
134 1 1
MISSING_ELSE
==> MISSING_ELSE
137 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
151 1 1
152 1 1
153 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
160 1 1
161 1 1
MISSING_ELSE
MISSING_ELSE
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
175 2 2
176 2 2
177 1 1
180 2 2
181 2 2
182 1 1
210 2 2
211 1 1
215 2 2
216 1 1
220 2 2
221 1 1
225 2 2
226 1 1


Cond Coverage for Module : prim_sha2_32
TotalCoveredPercent
Conditions716794.37
Logical716794.37
Non-Logical00
Event00

 LINE       42
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       70
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       73
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       74
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       75
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       89
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T5,T10
10CoveredT1,T2,T3

 LINE       92
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       99
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       112
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T5,T10
10CoveredT10,T6,T11

 LINE       115
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       124
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       129
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T5,T10
10CoveredT2,T10,T11

 LINE       132
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       140
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       142
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       142
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       142
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       148
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       153
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT2,T3,T10

 LINE       153
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       153
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T11
10CoveredT2,T3,T10

 LINE       157
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT11,T12,T8
1CoveredT2,T3,T10

 LINE       160
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       166
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT2,T3,T4

 LINE       180
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

Branch Coverage for Module : prim_sha2_32
Line No.TotalCoveredPercent
Branches 42 41 97.62
IF 70 2 2 100.00
IF 73 23 22 95.65
IF 166 3 3 100.00
IF 175 3 3 100.00
IF 180 3 3 100.00
IF 210 2 2 100.00
IF 215 2 2 100.00
IF 220 2 2 100.00
IF 225 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 if (((!sha_en_i) || hash_go))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 73 if ((sha_en_i && fifo_rvalid_i)) -2-: 74 if ((gen_multimode_logic.word_part_count_q == 2'b0)) -3-: 75 if ((gen_multimode_logic.digest_mode_flag_q != SHA2_256)) -4-: 89 if ((hash_process_i || gen_multimode_logic.process_flag_q)) -5-: 92 if ((sha_ready == 1'b1)) -6-: 99 if ((gen_multimode_logic.word_part_count_q == 2'b1)) -7-: 112 if ((hash_process_i || gen_multimode_logic.process_flag_q)) -8-: 115 if ((sha_ready == 1'b1)) -9-: 124 if ((gen_multimode_logic.word_part_count_q == 2'b10)) -10-: 129 if ((hash_process_i || gen_multimode_logic.process_flag_q)) -11-: 132 if ((sha_ready == 1'b1)) -12-: 137 if (sha_en_i) -13-: 140 if (((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))) -14-: 142 if (((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))) -15-: 148 if ((sha_ready == 1'b1)) -16-: 151 if ((gen_multimode_logic.word_part_count_q == 2'b1)) -17-: 153 if (((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))) -18-: 157 if ((sha_ready == 1'b1)) -19-: 160 if ((gen_multimode_logic.word_part_count_q == 2'b10))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19-StatusTests
1 1 1 - - - - - - - - - - - - - - - - Covered T2,T3,T4
1 1 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
1 1 0 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
1 1 0 - 1 - - - - - - - - - - - - - - Covered T1,T2,T3
1 1 0 - 0 - - - - - - - - - - - - - - Covered T1,T2,T3
1 0 - - - 1 1 - - - - - - - - - - - - Covered T2,T5,T10
1 0 - - - 1 0 - - - - - - - - - - - - Covered T2,T3,T4
1 0 - - - 1 - 1 - - - - - - - - - - - Covered T2,T3,T4
1 0 - - - 1 - 0 - - - - - - - - - - - Covered T2,T3,T4
1 0 - - - 0 - - 1 1 - - - - - - - - - Covered T2,T5,T10
1 0 - - - 0 - - 1 0 - - - - - - - - - Covered T2,T3,T4
1 0 - - - 0 - - 1 - 1 - - - - - - - - Covered T2,T3,T4
1 0 - - - 0 - - 1 - 0 - - - - - - - - Covered T2,T3,T4
1 0 - - - 0 - - 0 - - - - - - - - - - Not Covered
0 - - - - - - - - - - 1 1 - - - - - - Covered T1,T2,T3
0 - - - - - - - - - - 1 0 1 1 - - - - Covered T2,T3,T4
0 - - - - - - - - - - 1 0 1 0 - - - - Covered T2,T3,T4
0 - - - - - - - - - - 1 0 0 - 1 - - - Covered T2,T3,T4
0 - - - - - - - - - - 1 0 0 - 0 1 1 - Covered T2,T3,T10
0 - - - - - - - - - - 1 0 0 - 0 1 0 - Covered T11,T12,T8
0 - - - - - - - - - - 1 0 0 - 0 0 - 1 Covered T3,T4,T6
0 - - - - - - - - - - 1 0 0 - 0 0 - 0 Covered T1,T2,T3
0 - - - - - - - - - - 0 - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 166 if (((gen_multimode_logic.word_part_reset || hash_go) || (!sha_en_i))) -2-: 168 if (gen_multimode_logic.word_part_inc)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 175 if (hash_go) -2-: 176 if (hash_done_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 180 if (((!sha_en_i) || hash_go)) -2-: 181 if (hash_process_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 210 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 220 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 225 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%