Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21086037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22664168

1

T1

17015

T2

278

T3

8618

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17111303	1			T1	15009		T2	253		T3	5886
values[0x0]	12360182	1			T1	9838		T2	147		T3	3750
values[0x1]	14278720	1			T1	12345		T2	162		T3	3707

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15548712	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28201493

1

T1

22410

T2

340

T3

9938

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	157385	1			T1	139		T2	5		T3	10
valid_sources[0x01]	193840	1			T1	130		T2	2		T3	56
valid_sources[0x02]	166953	1			T1	146		T3	21		T4	270
valid_sources[0x03]	146956	1			T1	156		T2	5		T3	51
valid_sources[0x04]	170909	1			T1	145		T2	1		T3	24
valid_sources[0x05]	151037	1			T1	129		T2	2		T3	14
valid_sources[0x06]	164561	1			T1	124		T2	1		T3	48
valid_sources[0x07]	160116	1			T1	107		T2	9		T3	41
valid_sources[0x08]	142304	1			T1	114		T3	30		T4	244
valid_sources[0x09]	167154	1			T1	131		T3	15		T4	230
valid_sources[0x0a]	190668	1			T1	153		T3	2		T4	251
valid_sources[0x0b]	157618	1			T1	152		T3	38		T4	237
valid_sources[0x0c]	145205	1			T1	153		T2	3		T3	34
valid_sources[0x0d]	194488	1			T1	147		T3	40		T4	246
valid_sources[0x0e]	166300	1			T1	138		T3	91		T4	243
valid_sources[0x0f]	155307	1			T1	143		T2	8		T3	41
valid_sources[0x10]	167852	1			T1	111		T2	2		T3	1
valid_sources[0x11]	153268	1			T1	142		T2	1		T3	61
valid_sources[0x12]	175113	1			T1	130		T3	17		T4	224
valid_sources[0x13]	180145	1			T1	125		T3	17		T4	256
valid_sources[0x14]	183363	1			T1	149		T2	1		T3	36
valid_sources[0x15]	156721	1			T1	145		T2	6		T3	33
valid_sources[0x16]	150322	1			T1	124		T2	4		T3	24
valid_sources[0x17]	219734	1			T1	140		T3	30		T4	249
valid_sources[0x18]	144582	1			T1	148		T2	2		T3	23
valid_sources[0x19]	150723	1			T1	141		T2	7		T3	20
valid_sources[0x1a]	168145	1			T1	180		T2	1		T3	57
valid_sources[0x1b]	158450	1			T1	131		T3	45		T4	220
valid_sources[0x1c]	148876	1			T1	156		T3	6		T4	246
valid_sources[0x1d]	166258	1			T1	138		T3	29		T4	235
valid_sources[0x1e]	194217	1			T1	135		T3	73		T4	270
valid_sources[0x1f]	147899	1			T1	185		T2	1		T3	2
valid_sources[0x20]	143247	1			T1	157		T2	15		T3	32
valid_sources[0x21]	155013	1			T1	163		T2	15		T3	89
valid_sources[0x22]	167387	1			T1	133		T3	10		T4	224
valid_sources[0x23]	169538	1			T1	149		T2	6		T3	6
valid_sources[0x24]	170969	1			T1	136		T3	59		T4	245
valid_sources[0x25]	170576	1			T1	160		T3	19		T4	263
valid_sources[0x26]	167494	1			T1	135		T2	8		T3	44
valid_sources[0x27]	147433	1			T1	141		T2	11		T3	60
valid_sources[0x28]	163218	1			T1	130		T2	4		T3	7
valid_sources[0x29]	192927	1			T1	128		T2	2		T3	26
valid_sources[0x2a]	144323	1			T1	169		T3	4		T4	255
valid_sources[0x2b]	150352	1			T1	152		T3	40		T4	223
valid_sources[0x2c]	230692	1			T1	180		T2	1		T3	59
valid_sources[0x2d]	160720	1			T1	158		T3	21		T4	272
valid_sources[0x2e]	143906	1			T1	156		T2	3		T3	36
valid_sources[0x2f]	180504	1			T1	141		T3	33		T4	238
valid_sources[0x30]	158521	1			T1	142		T3	33		T4	240
valid_sources[0x31]	163805	1			T1	130		T3	15		T4	248
valid_sources[0x32]	164542	1			T1	117		T2	4		T3	24
valid_sources[0x33]	150228	1			T1	132		T2	1		T3	13
valid_sources[0x34]	184621	1			T1	145		T3	16		T4	216
valid_sources[0x35]	155479	1			T1	164		T2	3		T3	43
valid_sources[0x36]	161170	1			T1	140		T2	2		T3	3
valid_sources[0x37]	209585	1			T1	152		T3	65		T4	249
valid_sources[0x38]	211364	1			T1	126		T2	1		T3	14
valid_sources[0x39]	171546	1			T1	185		T3	32		T4	228
valid_sources[0x3a]	192334	1			T1	153		T3	40		T4	238
valid_sources[0x3b]	151308	1			T1	154		T2	1		T3	7
valid_sources[0x3c]	164430	1			T1	166		T3	34		T4	262
valid_sources[0x3d]	153050	1			T1	158		T2	8		T3	9
valid_sources[0x3e]	152997	1			T1	173		T2	1		T3	74
valid_sources[0x3f]	201522	1			T1	140		T3	14		T4	245
valid_sources[0x40]	177464	1			T1	137		T2	3		T3	21
valid_sources[0x41]	167149	1			T1	185		T2	4		T3	199
valid_sources[0x42]	186899	1			T1	178		T2	2		T3	134
valid_sources[0x43]	147118	1			T1	149		T3	16		T4	231
valid_sources[0x44]	166191	1			T1	140		T3	93		T4	208
valid_sources[0x45]	219856	1			T1	162		T2	3		T3	54
valid_sources[0x46]	187980	1			T1	156		T3	72		T4	247
valid_sources[0x47]	140770	1			T1	151		T2	6		T3	8
valid_sources[0x48]	185268	1			T1	146		T3	41		T4	235
valid_sources[0x49]	168347	1			T1	145		T2	3		T3	51
valid_sources[0x4a]	182990	1			T1	154		T2	1		T3	110
valid_sources[0x4b]	170715	1			T1	164		T3	12		T4	250
valid_sources[0x4c]	143132	1			T1	161		T2	1		T3	59
valid_sources[0x4d]	156474	1			T1	149		T2	1		T3	33
valid_sources[0x4e]	143775	1			T1	168		T3	31		T4	223
valid_sources[0x4f]	170943	1			T1	153		T2	12		T3	34
valid_sources[0x50]	154134	1			T1	168		T3	66		T4	227
valid_sources[0x51]	171157	1			T1	141		T2	1		T3	18
valid_sources[0x52]	171163	1			T1	117		T2	2		T3	184
valid_sources[0x53]	172276	1			T1	153		T2	2		T3	40
valid_sources[0x54]	168785	1			T1	142		T2	8		T3	6
valid_sources[0x55]	215104	1			T1	127		T2	3		T3	16
valid_sources[0x56]	204468	1			T1	132		T3	54		T4	251
valid_sources[0x57]	223405	1			T1	129		T2	4		T3	18
valid_sources[0x58]	161322	1			T1	151		T2	7		T3	16
valid_sources[0x59]	150880	1			T1	145		T3	8		T4	244
valid_sources[0x5a]	220996	1			T1	122		T3	60		T4	245
valid_sources[0x5b]	161169	1			T1	144		T3	73		T4	217
valid_sources[0x5c]	221881	1			T1	126		T2	4		T3	35
valid_sources[0x5d]	153086	1			T1	142		T2	4		T3	32
valid_sources[0x5e]	297393	1			T1	153		T3	25		T4	244
valid_sources[0x5f]	160948	1			T1	127		T2	1		T3	27
valid_sources[0x60]	191271	1			T1	132		T3	76		T4	230
valid_sources[0x61]	162502	1			T1	122		T3	31		T4	244
valid_sources[0x62]	191204	1			T1	138		T3	52		T4	231
valid_sources[0x63]	144238	1			T1	159		T3	30		T4	220
valid_sources[0x64]	154684	1			T1	177		T2	3		T3	58
valid_sources[0x65]	227846	1			T1	167		T2	3		T3	12
valid_sources[0x66]	156245	1			T1	153		T2	4		T3	33
valid_sources[0x67]	145206	1			T1	183		T3	26		T4	254
valid_sources[0x68]	148851	1			T1	139		T2	7		T3	1
valid_sources[0x69]	172935	1			T1	147		T2	1		T3	26
valid_sources[0x6a]	155103	1			T1	130		T3	72		T4	238
valid_sources[0x6b]	157177	1			T1	137		T2	2		T3	15
valid_sources[0x6c]	158559	1			T1	166		T3	20		T4	261
valid_sources[0x6d]	166435	1			T1	140		T3	31		T4	238
valid_sources[0x6e]	177875	1			T1	134		T2	6		T3	18
valid_sources[0x6f]	143037	1			T1	162		T2	4		T3	24
valid_sources[0x70]	144160	1			T1	126		T2	1		T3	102
valid_sources[0x71]	156876	1			T1	136		T3	36		T4	223
valid_sources[0x72]	225208	1			T1	172		T3	2		T4	209
valid_sources[0x73]	147763	1			T1	145		T2	8		T3	10
valid_sources[0x74]	185618	1			T1	156		T3	40		T4	243
valid_sources[0x75]	190426	1			T1	154		T3	43		T4	201
valid_sources[0x76]	180568	1			T1	145		T2	13		T3	45
valid_sources[0x77]	154553	1			T1	142		T3	84		T4	239
valid_sources[0x78]	158822	1			T1	143		T3	96		T4	246
valid_sources[0x79]	155889	1			T1	138		T2	4		T3	37
valid_sources[0x7a]	178573	1			T1	184		T2	8		T3	3566
valid_sources[0x7b]	153496	1			T1	146		T2	6		T3	37
valid_sources[0x7c]	163574	1			T1	159		T2	3		T3	48
valid_sources[0x7d]	161142	1			T1	161		T3	51		T4	239
valid_sources[0x7e]	164479	1			T1	132		T2	1		T3	80
valid_sources[0x7f]	173186	1			T1	156		T3	25		T4	226
valid_sources[0x80]	277876	1			T1	150		T2	4		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8471967

1

T1

7464

T2

121

T3

2288

values[0x0]

all_enables

biggest_size

7472549

1

T1

5069

T2

92

T3

3263

values[0x1]

all_enables

biggest_size

6719652

1

T1

4482

T2

65

T3

3067