Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24099331

1

T1

20177

T2

284

T3

4725

full_word

22858936

1

T1

17015

T2

278

T3

8618

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	46957857	1			T1	37192		T2	562		T3	13343
auto[TlIntgErrCmd]	127	1			T65	10		T66	6		T67	6
auto[TlIntgErrData]	147	1			T65	6		T66	13		T67	7
auto[TlIntgErrBoth]	136	1			T65	14		T66	11		T67	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18117645

1

T1

15009

T2

253

T3

5886

auto[1]

28840622

1

T1

22183

T2

309

T3

7457

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9568690	1			T1	7545		T2	132		T3	3598
auto[TlIntgErrNone]	partial	auto[1]	14530259	1			T1	12632		T2	152		T3	1127
auto[TlIntgErrNone]	full_word	auto[0]	8548767	1			T1	7464		T2	121		T3	2288
auto[TlIntgErrNone]	full_word	auto[1]	14310141	1			T1	9551		T2	157		T3	6330
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T65	3		T66	4		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T65	7		T66	1		T67	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T67	1		T135	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T66	1		T133	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T65	4		T66	7		T67	3
auto[TlIntgErrData]	partial	auto[1]	61	1			T65	1		T66	4		T67	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T65	1		T135	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T66	2		T67	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T65	6		T66	5		T67	3
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T65	7		T66	5		T67	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	2		T139	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T65	1		T66	1		T140	1