Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19335344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20161405

1

T1

3386

T2

1879

T3

2194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15787351	1			T1	3041		T2	1339		T3	1873
values[0x0]	11050806	1			T1	1977		T2	721		T3	877
values[0x1]	12658592	1			T1	2448		T2	848		T3	959

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14359281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25137468

1

T1

4446

T2

2144

T3

2619

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257637	1			T1	28		T2	7		T4	563
valid_sources[0x01]	145246	1			T1	37		T2	11		T4	963
valid_sources[0x02]	147823	1			T1	36		T2	6		T3	9
valid_sources[0x03]	134086	1			T1	27		T2	18		T4	438
valid_sources[0x04]	127849	1			T1	28		T2	14		T4	453
valid_sources[0x05]	139111	1			T1	31		T2	10		T4	770
valid_sources[0x06]	124842	1			T1	38		T2	9		T4	572
valid_sources[0x07]	125567	1			T1	29		T2	8		T3	22
valid_sources[0x08]	196892	1			T1	24		T2	9		T4	612
valid_sources[0x09]	147091	1			T1	36		T2	7		T3	5
valid_sources[0x0a]	134714	1			T1	27		T2	19		T3	5
valid_sources[0x0b]	126451	1			T1	27		T2	21		T4	961
valid_sources[0x0c]	155471	1			T1	34		T2	7		T4	413
valid_sources[0x0d]	125874	1			T1	28		T2	6		T4	580
valid_sources[0x0e]	126908	1			T1	32		T2	10		T4	624
valid_sources[0x0f]	159348	1			T1	29		T2	12		T4	463
valid_sources[0x10]	278224	1			T1	29		T2	12		T4	1307
valid_sources[0x11]	147972	1			T1	28		T2	7		T4	724
valid_sources[0x12]	126218	1			T1	24		T2	4		T4	683
valid_sources[0x13]	136704	1			T1	25		T2	17		T4	591
valid_sources[0x14]	177109	1			T1	23		T2	11		T4	891
valid_sources[0x15]	170782	1			T1	35		T2	12		T4	1094
valid_sources[0x16]	133029	1			T1	42		T2	15		T4	734
valid_sources[0x17]	149608	1			T1	24		T2	11		T4	915
valid_sources[0x18]	157885	1			T1	29		T2	24		T4	879
valid_sources[0x19]	169600	1			T1	42		T2	12		T4	611
valid_sources[0x1a]	155420	1			T1	34		T2	13		T3	9
valid_sources[0x1b]	150002	1			T1	17		T2	15		T3	14
valid_sources[0x1c]	127518	1			T1	31		T2	9		T4	731
valid_sources[0x1d]	147332	1			T1	49		T2	21		T4	712
valid_sources[0x1e]	167872	1			T1	24		T2	9		T4	722
valid_sources[0x1f]	141958	1			T1	26		T2	6		T4	581
valid_sources[0x20]	128755	1			T1	31		T2	5		T4	968
valid_sources[0x21]	134018	1			T1	32		T2	13		T4	660
valid_sources[0x22]	177210	1			T1	34		T2	16		T4	501
valid_sources[0x23]	143543	1			T1	25		T2	22		T4	505
valid_sources[0x24]	140931	1			T1	28		T2	3		T3	1
valid_sources[0x25]	132080	1			T1	35		T2	4		T4	815
valid_sources[0x26]	137556	1			T1	23		T2	11		T4	478
valid_sources[0x27]	152699	1			T1	23		T2	14		T4	843
valid_sources[0x28]	207596	1			T1	32		T2	5		T4	674
valid_sources[0x29]	149840	1			T1	30		T2	13		T4	572
valid_sources[0x2a]	132656	1			T1	27		T2	14		T4	497
valid_sources[0x2b]	125899	1			T1	30		T4	645		T5	19
valid_sources[0x2c]	127977	1			T1	39		T2	11		T4	781
valid_sources[0x2d]	140403	1			T1	33		T2	5		T4	692
valid_sources[0x2e]	135914	1			T1	33		T2	2		T3	1
valid_sources[0x2f]	126934	1			T1	29		T2	13		T4	504
valid_sources[0x30]	154262	1			T1	31		T2	12		T4	630
valid_sources[0x31]	179076	1			T1	47		T2	1		T4	735
valid_sources[0x32]	127157	1			T1	36		T2	20		T4	604
valid_sources[0x33]	139736	1			T1	45		T2	8		T4	759
valid_sources[0x34]	142415	1			T1	34		T2	1		T4	733
valid_sources[0x35]	244364	1			T1	29		T2	15		T3	1
valid_sources[0x36]	161771	1			T1	34		T2	14		T4	483
valid_sources[0x37]	181458	1			T1	18		T2	15		T4	767
valid_sources[0x38]	159770	1			T1	25		T2	8		T4	474
valid_sources[0x39]	137340	1			T1	37		T2	14		T4	694
valid_sources[0x3a]	145318	1			T1	28		T2	22		T3	119
valid_sources[0x3b]	136120	1			T1	32		T2	28		T4	326
valid_sources[0x3c]	138489	1			T1	30		T2	10		T3	9
valid_sources[0x3d]	144681	1			T1	21		T2	10		T4	637
valid_sources[0x3e]	130280	1			T1	22		T2	10		T4	875
valid_sources[0x3f]	145769	1			T1	24		T2	8		T4	1090
valid_sources[0x40]	172207	1			T1	33		T2	6		T4	774
valid_sources[0x41]	218743	1			T1	30		T2	13		T4	392
valid_sources[0x42]	173524	1			T1	27		T2	7		T3	139
valid_sources[0x43]	167394	1			T1	18		T2	4		T4	792
valid_sources[0x44]	178597	1			T1	30		T2	1		T4	726
valid_sources[0x45]	210025	1			T1	35		T2	18		T3	83
valid_sources[0x46]	142306	1			T1	31		T2	4		T4	689
valid_sources[0x47]	200413	1			T1	37		T2	14		T4	1014
valid_sources[0x48]	155870	1			T1	26		T2	8		T4	459
valid_sources[0x49]	147497	1			T1	33		T2	1		T4	723
valid_sources[0x4a]	207022	1			T1	33		T2	15		T3	2
valid_sources[0x4b]	165887	1			T1	25		T2	9		T4	988
valid_sources[0x4c]	166254	1			T1	27		T2	6		T4	658
valid_sources[0x4d]	133211	1			T1	31		T2	10		T4	451
valid_sources[0x4e]	167366	1			T1	28		T2	12		T4	693
valid_sources[0x4f]	133031	1			T1	32		T2	18		T4	562
valid_sources[0x50]	161631	1			T1	19		T2	11		T4	707
valid_sources[0x51]	130730	1			T1	33		T2	12		T4	684
valid_sources[0x52]	171704	1			T1	35		T2	9		T4	713
valid_sources[0x53]	158180	1			T1	32		T2	2		T4	617
valid_sources[0x54]	190189	1			T1	32		T2	28		T4	708
valid_sources[0x55]	215815	1			T1	33		T2	10		T3	5
valid_sources[0x56]	148500	1			T1	28		T2	13		T4	771
valid_sources[0x57]	128749	1			T1	49		T2	20		T4	460
valid_sources[0x58]	130386	1			T1	25		T2	9		T4	697
valid_sources[0x59]	135694	1			T1	36		T2	13		T4	999
valid_sources[0x5a]	149032	1			T1	33		T2	9		T3	5
valid_sources[0x5b]	163616	1			T1	32		T2	14		T4	533
valid_sources[0x5c]	128762	1			T1	16		T2	7		T4	794
valid_sources[0x5d]	145210	1			T1	32		T2	11		T4	759
valid_sources[0x5e]	128395	1			T1	36		T2	7		T4	492
valid_sources[0x5f]	145333	1			T1	25		T2	7		T4	730
valid_sources[0x60]	137838	1			T1	32		T2	16		T4	942
valid_sources[0x61]	137856	1			T1	36		T2	8		T4	387
valid_sources[0x62]	202602	1			T1	17		T2	11		T3	9
valid_sources[0x63]	126098	1			T1	25		T2	23		T4	756
valid_sources[0x64]	139128	1			T1	23		T2	10		T3	10
valid_sources[0x65]	131965	1			T1	40		T2	18		T4	666
valid_sources[0x66]	127233	1			T1	34		T2	15		T4	774
valid_sources[0x67]	160306	1			T1	39		T2	10		T4	731
valid_sources[0x68]	155285	1			T1	24		T2	4		T4	521
valid_sources[0x69]	137589	1			T1	27		T2	7		T4	880
valid_sources[0x6a]	158661	1			T1	29		T2	6		T4	501
valid_sources[0x6b]	131376	1			T1	32		T2	6		T4	371
valid_sources[0x6c]	170303	1			T1	26		T2	14		T4	838
valid_sources[0x6d]	146833	1			T1	26		T2	8		T4	635
valid_sources[0x6e]	187779	1			T1	37		T2	3		T4	460
valid_sources[0x6f]	159210	1			T1	20		T2	12		T4	1169
valid_sources[0x70]	161789	1			T1	21		T2	15		T3	285
valid_sources[0x71]	173810	1			T1	25		T2	13		T4	834
valid_sources[0x72]	140391	1			T1	25		T2	10		T4	787
valid_sources[0x73]	128712	1			T1	43		T2	12		T4	697
valid_sources[0x74]	192247	1			T1	30		T2	7		T4	657
valid_sources[0x75]	129618	1			T1	22		T2	17		T4	448
valid_sources[0x76]	134354	1			T1	34		T2	19		T4	534
valid_sources[0x77]	155462	1			T1	29		T2	14		T4	824
valid_sources[0x78]	144691	1			T1	27		T2	8		T3	373
valid_sources[0x79]	197487	1			T1	28		T2	10		T4	780
valid_sources[0x7a]	178803	1			T1	29		T2	25		T4	579
valid_sources[0x7b]	127986	1			T1	29		T2	9		T4	750
valid_sources[0x7c]	143201	1			T1	24		T2	13		T4	680
valid_sources[0x7d]	189733	1			T1	27		T2	12		T3	38
valid_sources[0x7e]	153211	1			T1	29		T2	26		T4	520
valid_sources[0x7f]	126813	1			T1	23		T2	12		T3	5
valid_sources[0x80]	142898	1			T1	31		T4	543		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7753441

1

T1

1505

T2

659

T3

746

values[0x0]

all_enables

biggest_size

6549242

1

T1

961

T2

574

T3

716

values[0x1]

all_enables

biggest_size

5858722

1

T1

920

T2

646

T3

732