Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

19643466

1

T1

4080

T2

1029

T3

1515

full_word

20181679

1

T1

3386

T2

1879

T3

2194

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	39824705	1			T1	7466		T2	2908		T3	3709
auto[TlIntgErrCmd]	164	1			T59	5		T60	8		T61	5
auto[TlIntgErrData]	141	1			T59	7		T60	5		T61	8
auto[TlIntgErrBoth]	135	1			T59	8		T60	7		T61	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15894825

1

T1

3041

T2

1339

T3

1873

auto[1]

23930320

1

T1

4425

T2

1569

T3

1836

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8132998	1			T1	1536		T2	680		T3	1127
auto[TlIntgErrNone]	partial	auto[1]	11510079	1			T1	2544		T2	349		T3	388
auto[TlIntgErrNone]	full_word	auto[0]	7761622	1			T1	1505		T2	659		T3	746
auto[TlIntgErrNone]	full_word	auto[1]	12420006	1			T1	1881		T2	1220		T3	1448
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T59	1		T60	3		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T59	3		T60	5		T86	6
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T61	1		T86	3		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	14	1			T59	1		T61	1		T86	2
auto[TlIntgErrData]	partial	auto[0]	67	1			T59	3		T60	3		T61	7
auto[TlIntgErrData]	partial	auto[1]	59	1			T59	3		T61	1		T86	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T59	1		T60	1		T86	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T60	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T59	3		T60	3		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T59	3		T60	4		T61	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T59	1		T115	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T59	1		T118	1		T113	1