Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	191626720	174268	0	0
intr_enable_rd_A	191626720	1294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191626720	174268	0	0
T27	9442	21	0	0
T28	3698	7	0	0
T29	6971	189	0	0
T56	4903	600	0	0
T57	3929	496	0	0
T58	3363	20	0	0
T59	15250	3	0	0
T60	15363	4	0	0
T67	4588	27	0	0
T72	4158	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191626720	1294	0	0
T19	663619	26	0	0
T20	290227	0	0	0
T23	1376	0	0	0
T24	1186	0	0	0
T27	0	22	0	0
T70	0	27	0	0
T73	0	9	0	0
T74	0	28	0	0
T75	0	6	0	0
T76	0	17	0	0
T77	0	8	0	0
T78	0	6	0	0
T79	0	11	0	0
T80	5228	0	0	0
T81	436698	0	0	0
T82	23971	0	0	0
T83	219188	0	0	0
T84	119959	0	0	0
T85	123594	0	0	0