Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43168388

1

T1

12416

T2

49128

T3

389481

full_word

41468646

1

T1

10516

T2

49703

T3

410965

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84636644	1			T1	22932		T2	98831		T3	800446
auto[TlIntgErrCmd]	113	1			T53	3		T54	7		T55	2
auto[TlIntgErrData]	136	1			T54	6		T55	3		T121	9
auto[TlIntgErrBoth]	141	1			T53	7		T54	7		T55	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33763661

1

T1

9206

T2

44367

T3

302397

auto[1]

50873373

1

T1

13726

T2

54464

T3

498049

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17690687	1			T1	4586		T2	22026		T3	152802
auto[TlIntgErrNone]	partial	auto[1]	25477347	1			T1	7830		T2	27102		T3	236679
auto[TlIntgErrNone]	full_word	auto[0]	16072786	1			T1	4620		T2	22341		T3	149595
auto[TlIntgErrNone]	full_word	auto[1]	25395824	1			T1	5896		T2	27362		T3	261370
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T54	3		T55	1		T121	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T53	3		T54	4		T55	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T121	1		T122	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T123	1		T119	1		T124	2
auto[TlIntgErrData]	partial	auto[0]	70	1			T54	4		T55	1		T121	5
auto[TlIntgErrData]	partial	auto[1]	56	1			T54	1		T55	2		T121	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T121	1		T123	2		T59	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T54	1		T121	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T53	2		T54	2		T55	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T53	4		T54	5		T55	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T53	1		T123	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T121	1		T119	1		T122	1