Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

35317277

1

T1

306

T2

38658

T3

187872

full_word

34357472

1

T1

310

T2

33486

T3

187841

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69674359	1			T1	616		T2	72144		T3	375713
auto[TlIntgErrCmd]	132	1			T55	3		T56	6		T57	12
auto[TlIntgErrData]	125	1			T55	2		T56	8		T57	4
auto[TlIntgErrBoth]	133	1			T55	5		T56	6		T57	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27857915

1

T1

317

T2

29359

T3

148577

auto[1]

41816834

1

T1

299

T2

42785

T3

227136

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14470357	1			T1	160		T2	14582		T3	74482
auto[TlIntgErrNone]	partial	auto[1]	20846562	1			T1	146		T2	24076		T3	113390
auto[TlIntgErrNone]	full_word	auto[0]	13387387	1			T1	157		T2	14777		T3	74095
auto[TlIntgErrNone]	full_word	auto[1]	20970053	1			T1	153		T2	18709		T3	113746
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T56	1		T57	4		T127	1
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T55	3		T56	4		T57	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T56	1		T129	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T57	2		T130	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T55	2		T56	4		T57	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T56	3		T57	2		T127	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T131	2		T128	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T56	1		T127	2		T133	2
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T55	1		T56	3		T57	8
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T55	4		T56	3		T57	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T134	1		T135	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T136	1		T130	1		T137	1