Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	347337483	1260376	0	0
intr_enable_rd_A	347337483	3022	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347337483	1260376	0	0
T10	436895	189866	0	0
T11	0	46590	0	0
T12	0	157991	0	0
T13	0	58165	0	0
T28	0	48302	0	0
T63	0	16	0	0
T65	0	367	0	0
T66	0	271745	0	0
T67	0	14	0	0
T68	0	10	0	0
T69	420028	0	0	0
T70	420923	0	0	0
T71	45535	0	0	0
T72	25157	0	0	0
T73	77885	0	0	0
T74	52774	0	0	0
T75	246335	0	0	0
T76	3403	0	0	0
T77	4588	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347337483	3022	0	0
T62	0	234	0	0
T63	0	8	0	0
T67	0	29	0	0
T78	254028	12	0	0
T79	0	19	0	0
T80	0	68	0	0
T81	0	44	0	0
T82	0	56	0	0
T83	0	7	0	0
T84	0	12	0	0
T85	5402	0	0	0
T86	1264	0	0	0
T87	3873	0	0	0
T88	480889	0	0	0
T89	2699	0	0	0
T90	27949	0	0	0
T91	846857	0	0	0
T92	111711	0	0	0
T93	764270	0	0	0