Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.46	95.45	90.16		100.00	88.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	93.46	95.45	90.16		100.00	88.24

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.46	95.45	90.16		100.00	88.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.46	95.45	90.16		100.00	88.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		154	147	95.45
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ALWAYS	133	21	21	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	208	16	15	93.75
CONT_ASSIGN	232	1	1	100.00
ALWAYS	235	4	4	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	251	10	6	60.00
ALWAYS	269	3	3	100.00
ALWAYS	275	6	6	100.00
ALWAYS	285	4	4	100.00
ALWAYS	293	6	6	100.00
CONT_ASSIGN	302	1	1	100.00
ALWAYS	305	3	3	100.00
ALWAYS	310	64	62	96.88
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
ALWAYS	452	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
125	1	1
126	1	1
128	1	1
129	1	1
133	1	1
135	1	1
137	1	1
139	1	1
141	1	1
145	1	1
147	1	1
149	1	1
151	1	1
155	1	1
157	1	1
159	1	1
161	1	1
165	1	1
166	1	1
168	1	1
169	1	1
174	1	1
175	1	1
177	1	1
178	1	1
189	1	1
191	1	1
192	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
219	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
229	0	1
232	1	1
235	1	1
236	1	1
237	1	1
238	1	1
243	1	1
251	1	1
252	1	1
253	1	1
254	1	1
257	0	1
258	0	1
259	0	1
260	0	1
263	1	1
264	1	1
			MISSING_ELSE
269	2	2
270	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			==> MISSING_ELSE
302	1	1
305	2	2
306	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
324	1	1
326	1	1
327	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
339	1	1
341	1	1
342	1	1
344	1	1
346	1	1
348	1	1
353	1	1
354	1	1
356	1	1
357	0	1
358	0	1
			MISSING_ELSE
361	1	1
363	1	1
364	1	1
365	1	1
367	1	1
368	1	1
373	1	1
375	1	1
376	1	1
377	1	1
379	1	1
382	1	1
387	1	1
388	1	1
389	1	1
390	1	1
392	1	1
396	1	1
398	1	1
399	1	1
400	1	1
401	1	1
403	1	1
409	1	1
410	1	1
412	1	1
413	1	1
415	1	1
417	1	1
419	1	1
425	1	1
427	1	1
439	1	1
449	1	1
452	1	1
453	1	1
455	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	183	165	90.16
Logical	183	165	90.16
Non-Logical	0	0
Event	0	0

 LINE       122
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       123
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       189
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       189
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       189
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       191
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T5,T6

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T5

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T5,T6

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       213
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       214
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T5

 LINE       216
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T9
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T4,T5

 LINE       219
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       221
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T5

 LINE       223
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       225
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       236
 EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       238
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       243
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       279
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T4

 LINE       297
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       302
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       302
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       354
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       356
 EXPRESSION ((round_q == Inner) && reg_hash_continue_i)
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       356
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       361
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       361
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       361
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       361
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       361
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       365
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       376
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       392
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       392
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T2,T5,T6
0	1	0	Covered	T2,T4,T5
1	0	0	Covered	T1,T2,T5

 LINE       392
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T5

 LINE       392
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       392
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T5

 LINE       392
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       392
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       392
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T4,T5

 LINE       392
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T5,T6

 LINE       392
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       392
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T5,T6

 LINE       439
 EXPRESSION 
 Number  Term
      1  (reg_hash_start_i || reg_hash_continue_i) ? 1'b0 : ((st_q == StIdle) ? 1'b1 : (((st_q == StMsg) && txcnt_eq_blksz && reg_hash_stop_i) ? 1'b1 : idle_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       439
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       439
 SUB-EXPRESSION ((st_q == StIdle) ? 1'b1 : (((st_q == StMsg) && txcnt_eq_blksz && reg_hash_stop_i) ? 1'b1 : idle_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       439
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       439
 SUB-EXPRESSION (((st_q == StMsg) && txcnt_eq_blksz && reg_hash_stop_i) ? 1'b1 : idle_q)
                 ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       439
 SUB-EXPRESSION ((st_q == StMsg) && txcnt_eq_blksz && reg_hash_stop_i)
                 -------1-------    -------2------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T4
1	1	1	Not Covered

 LINE       439
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	377	Covered	T1,T2,T4
StIPad	327	Covered	T1,T2,T4
StIdle	334	Covered	T1,T2,T3
StMsg	342	Covered	T1,T2,T4
StOPad	396	Covered	T1,T2,T4
StPushToMsgFifo	379	Covered	T1,T2,T4
StWaitResp	363	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	425	Covered	T1,T2,T4
StIPad->StMsg	342	Covered	T1,T2,T4
StIdle->StIPad	327	Covered	T1,T2,T4
StMsg->StWaitResp	363	Covered	T1,T2,T4
StOPad->StMsg	413	Covered	T1,T2,T4
StPushToMsgFifo->StOPad	396	Covered	T1,T2,T4
StWaitResp->StDone	377	Covered	T1,T2,T4
StWaitResp->StPushToMsgFifo	379	Covered	T1,T2,T4

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		85	75	88.24
TERNARY	122	2	2	100.00
TERNARY	123	2	2	100.00
TERNARY	125	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	192	7	6	85.71
TERNARY	302	2	2	100.00
TERNARY	439	4	3	75.00
CASE	133	6	6	100.00
IF	209	9	8	88.89
CASE	235	4	4	100.00
IF	252	7	3	42.86
IF	269	2	2	100.00
IF	275	4	4	100.00
IF	285	3	3	100.00
IF	293	4	3	75.00
IF	305	2	2	100.00
CASE	324	17	15	88.24
IF	452	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	122	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	((!hmac_en_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	192	((!hmac_en_i)) ? 
-2-:	192	(((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? 
-3-:	192	(((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-4-:	192	(((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? 
-5-:	192	(((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-6-:	192	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	-	Covered	T2,T4,T5
0	0	0	1	-	-	Covered	T1,T2,T5
0	0	0	0	1	-	Covered	T2,T4,T5
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	302	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	439	((reg_hash_start_i || reg_hash_continue_i)) ? 
-2-:	439	((st_q == StIdle)) ? 
-3-:	439	((((st_q == StMsg) && txcnt_eq_blksz) && reg_hash_stop_i)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	133	case (key_length_i)

Branches:

-1-	Status	Tests
Key_128	Covered	T2,T5,T6
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T5,T6
Key_512	Covered	T2,T4,T5
Key_1024	Covered	T2,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!hmac_en_i))
-2-:	213	if ((sel_msglen == SelIPadMsg))
-3-:	214	if ((digest_size_i == SHA2_256))
-4-:	216	if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
-5-:	219	if ((sel_msglen == SelOPadMsg))
-6-:	221	if ((digest_size_i == SHA2_256))
-7-:	223	if ((digest_size_i == SHA2_384))
-8-:	225	if ((digest_size_i == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T2,T5
0	1	0	1	-	-	-	-	Covered	T2,T4,T5
0	1	0	0	-	-	-	-	Covered	T2,T5,T9
0	0	-	-	1	1	-	-	Covered	T1,T2,T5
0	0	-	-	1	0	1	-	Covered	T2,T5,T6
0	0	-	-	1	0	0	1	Covered	T2,T4,T5
0	0	-	-	1	0	0	0	Covered	T2,T4,T5
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	235	case (digest_size_i)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T2,T5,T6
SHA2_512	Covered	T2,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	if (clr_txcount)
-2-:	254	if (load_txcount)
-3-:	257	case (digest_size_i)
-4-:	263	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	SHA2_256	-	Not Covered
0	1	SHA2_384	-	Not Covered
0	1	SHA2_512	-	Not Covered
0	1	default	-	Not Covered
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	275	if ((!rst_ni))
-2-:	277	if (reg_hash_process_i)
-3-:	279	if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	285	if ((!rst_ni))
-2-:	287	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))
-2-:	295	if (clr_fifo_wdata_sel)
-3-:	297	if ((fifo_wsel_o && fifo_wvalid_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	case (st_q)
-2-:	326	if ((hmac_en_i && reg_hash_start_i))
-3-:	341	if (txcnt_eq_blksz)
-4-:	356	if (((round_q == Inner) && reg_hash_continue_i))
-5-:	361	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o)))
-6-:	375	if (sha_hash_done_i)
-7-:	376	if ((round_q == Outer))
-8-:	392	if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))))
-9-:	412	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T1,T2,T4
StIPad	-	0	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	1	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	0	-	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	1	1	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	1	0	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	0	-	-	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
StDone	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	452	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3