Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38005210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39550437

1

T1

2859

T2

3

T3

17487

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31325927	1			T1	2505		T2	1		T3	15456
values[0x0]	21529321	1			T1	1556		T2	3		T3	10141
values[0x1]	24700399	1			T1	1970		T2	7		T3	12583

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28252980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49302667

1

T1

3742

T2

5

T3

23163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	279329	1			T1	32		T3	11		T4	1
valid_sources[0x01]	345226	1			T1	22		T3	85		T4	4
valid_sources[0x02]	292020	1			T1	32		T3	168		T4	18
valid_sources[0x03]	262797	1			T1	28		T3	50		T6	53
valid_sources[0x04]	305349	1			T1	45		T3	87		T6	49
valid_sources[0x05]	288481	1			T1	19		T3	18		T6	53
valid_sources[0x06]	405330	1			T1	31		T3	87		T4	1
valid_sources[0x07]	287573	1			T1	37		T3	60		T4	3
valid_sources[0x08]	299645	1			T1	21		T3	53		T4	5
valid_sources[0x09]	285206	1			T1	16		T3	76		T4	3
valid_sources[0x0a]	297286	1			T1	24		T3	3		T4	1
valid_sources[0x0b]	317034	1			T1	24		T3	3		T6	55
valid_sources[0x0c]	262725	1			T1	22		T3	29		T4	3
valid_sources[0x0d]	272613	1			T1	17		T3	180		T4	1
valid_sources[0x0e]	305743	1			T1	31		T3	102		T4	2
valid_sources[0x0f]	306056	1			T1	22		T3	66		T4	2
valid_sources[0x10]	297877	1			T1	15		T3	65		T4	1
valid_sources[0x11]	286986	1			T1	16		T3	61		T5	1
valid_sources[0x12]	311898	1			T1	36		T3	73		T4	3
valid_sources[0x13]	259698	1			T1	35		T3	62		T4	1
valid_sources[0x14]	348948	1			T1	23		T3	105		T4	1
valid_sources[0x15]	298779	1			T1	20		T3	61		T6	46
valid_sources[0x16]	304209	1			T1	25		T3	69		T4	5
valid_sources[0x17]	257234	1			T1	33		T3	38		T4	2
valid_sources[0x18]	279230	1			T1	21		T3	71		T4	3
valid_sources[0x19]	312788	1			T1	22		T3	33		T4	3
valid_sources[0x1a]	386057	1			T1	30		T3	55		T4	1
valid_sources[0x1b]	290389	1			T1	18		T3	71		T4	2
valid_sources[0x1c]	335170	1			T1	21		T3	87		T4	5
valid_sources[0x1d]	299410	1			T1	31		T3	36		T4	2
valid_sources[0x1e]	300796	1			T1	27		T3	51		T4	5
valid_sources[0x1f]	301934	1			T1	32		T3	87		T4	3
valid_sources[0x20]	289535	1			T1	29		T3	22		T4	1
valid_sources[0x21]	311464	1			T1	15		T3	21		T4	3
valid_sources[0x22]	261084	1			T1	23		T3	6		T4	2
valid_sources[0x23]	302644	1			T1	17		T3	76		T4	4
valid_sources[0x24]	264745	1			T1	31		T3	78		T6	45
valid_sources[0x25]	285921	1			T1	27		T3	22		T6	55
valid_sources[0x26]	288992	1			T1	26		T3	31		T4	2
valid_sources[0x27]	328024	1			T1	21		T3	85		T4	5
valid_sources[0x28]	325158	1			T1	24		T3	60		T4	4
valid_sources[0x29]	319170	1			T1	33		T3	100		T4	1
valid_sources[0x2a]	272809	1			T1	17		T3	85		T4	6
valid_sources[0x2b]	385775	1			T1	30		T3	54		T4	6
valid_sources[0x2c]	303806	1			T1	20		T3	104		T4	2
valid_sources[0x2d]	324773	1			T1	10		T3	71		T4	1
valid_sources[0x2e]	353699	1			T1	23		T3	73		T4	8
valid_sources[0x2f]	418990	1			T1	20		T3	41		T5	1
valid_sources[0x30]	277118	1			T1	25		T3	70		T4	6
valid_sources[0x31]	328077	1			T1	25		T3	21		T4	4
valid_sources[0x32]	329368	1			T1	19		T3	22		T4	1
valid_sources[0x33]	283168	1			T1	21		T3	17		T6	64
valid_sources[0x34]	263886	1			T1	35		T3	37		T4	1
valid_sources[0x35]	287244	1			T1	27		T3	131		T4	4
valid_sources[0x36]	296853	1			T1	20		T3	68		T4	2
valid_sources[0x37]	320558	1			T1	24		T3	58		T4	4
valid_sources[0x38]	257412	1			T1	26		T3	14		T6	52
valid_sources[0x39]	318827	1			T1	20		T3	141		T4	3
valid_sources[0x3a]	395695	1			T1	18		T3	38		T6	39
valid_sources[0x3b]	320107	1			T1	42		T3	78		T4	7
valid_sources[0x3c]	305874	1			T1	16		T3	72		T4	1
valid_sources[0x3d]	359297	1			T1	26		T3	28		T5	5
valid_sources[0x3e]	284976	1			T1	29		T3	27		T4	2
valid_sources[0x3f]	314887	1			T1	18		T3	30		T4	1
valid_sources[0x40]	295991	1			T1	33		T3	20		T4	10
valid_sources[0x41]	276496	1			T1	30		T3	152		T6	49
valid_sources[0x42]	316065	1			T1	28		T3	57		T4	4
valid_sources[0x43]	285750	1			T1	23		T3	86		T4	1
valid_sources[0x44]	331815	1			T1	22		T3	24		T4	2
valid_sources[0x45]	302320	1			T1	19		T3	26		T4	4
valid_sources[0x46]	289609	1			T1	15		T3	91		T4	2
valid_sources[0x47]	291392	1			T1	41		T3	91		T4	4
valid_sources[0x48]	263941	1			T1	20		T3	12		T4	1
valid_sources[0x49]	388678	1			T1	28		T3	39		T4	8
valid_sources[0x4a]	308265	1			T1	18		T3	60		T4	5
valid_sources[0x4b]	287780	1			T1	21		T3	153		T4	1
valid_sources[0x4c]	285090	1			T1	18		T3	66		T6	57
valid_sources[0x4d]	325895	1			T1	22		T3	29		T4	5
valid_sources[0x4e]	300667	1			T1	31		T3	61		T4	2
valid_sources[0x4f]	309773	1			T1	23		T3	47		T5	9
valid_sources[0x50]	292889	1			T1	17		T3	112		T4	2
valid_sources[0x51]	329973	1			T1	28		T3	119		T4	2
valid_sources[0x52]	410861	1			T1	27		T3	13		T4	2
valid_sources[0x53]	300912	1			T1	21		T3	8		T6	54
valid_sources[0x54]	284517	1			T1	12		T3	29		T4	4
valid_sources[0x55]	270162	1			T1	23		T3	22		T4	3
valid_sources[0x56]	293471	1			T1	16		T3	76		T4	6
valid_sources[0x57]	282038	1			T1	18		T3	99		T5	13
valid_sources[0x58]	265684	1			T1	40		T3	41		T4	2
valid_sources[0x59]	298927	1			T1	36		T3	94		T4	1
valid_sources[0x5a]	347109	1			T1	26		T3	16768		T4	2
valid_sources[0x5b]	297704	1			T1	5		T3	161		T4	1
valid_sources[0x5c]	262816	1			T1	23		T3	50		T4	2
valid_sources[0x5d]	295432	1			T1	30		T3	106		T4	1
valid_sources[0x5e]	257140	1			T1	33		T3	41		T4	2
valid_sources[0x5f]	256077	1			T1	24		T3	38		T4	4
valid_sources[0x60]	266295	1			T1	21		T3	79		T4	4
valid_sources[0x61]	306007	1			T1	34		T3	87		T5	84
valid_sources[0x62]	259084	1			T1	32		T3	87		T4	4
valid_sources[0x63]	319528	1			T1	34		T3	78		T4	3
valid_sources[0x64]	285216	1			T1	16		T3	42		T4	1
valid_sources[0x65]	259261	1			T1	30		T3	73		T4	1
valid_sources[0x66]	383958	1			T1	28		T3	81		T4	1
valid_sources[0x67]	282408	1			T1	16		T3	33		T6	46
valid_sources[0x68]	262864	1			T1	14		T3	138		T4	6
valid_sources[0x69]	436900	1			T1	16		T3	71		T4	1
valid_sources[0x6a]	369782	1			T1	25		T3	20		T6	59
valid_sources[0x6b]	262957	1			T1	26		T3	17		T4	3
valid_sources[0x6c]	330020	1			T1	31		T3	82		T6	48
valid_sources[0x6d]	302668	1			T1	16		T3	8		T4	1
valid_sources[0x6e]	335448	1			T1	10		T3	41		T6	49
valid_sources[0x6f]	262581	1			T1	31		T3	3451		T4	8
valid_sources[0x70]	280408	1			T1	26		T3	77		T6	67
valid_sources[0x71]	280171	1			T1	12		T3	66		T4	2
valid_sources[0x72]	301097	1			T1	16		T3	38		T4	2
valid_sources[0x73]	267147	1			T1	16		T3	74		T6	60
valid_sources[0x74]	316582	1			T1	31		T3	112		T4	3
valid_sources[0x75]	327148	1			T1	38		T3	31		T4	1
valid_sources[0x76]	264234	1			T1	26		T3	24		T4	4
valid_sources[0x77]	275363	1			T1	21		T3	36		T4	1
valid_sources[0x78]	264585	1			T1	25		T3	88		T4	1
valid_sources[0x79]	307316	1			T1	24		T3	49		T4	4
valid_sources[0x7a]	311455	1			T1	34		T3	88		T6	57
valid_sources[0x7b]	318073	1			T1	22		T3	83		T4	1
valid_sources[0x7c]	287135	1			T1	31		T3	73		T4	1
valid_sources[0x7d]	272879	1			T1	23		T3	75		T4	1
valid_sources[0x7e]	314488	1			T1	24		T3	33		T4	1
valid_sources[0x7f]	256302	1			T1	13		T3	30		T4	5
valid_sources[0x80]	349249	1			T1	18		T3	61		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15418324

1

T1

1300

T2

1

T3

7741

values[0x0]

all_enables

biggest_size

12752563

1

T1

821

T2

1

T3

5201

values[0x1]

all_enables

biggest_size

11379550

1

T1

738

T2

1

T3

4545