Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 39673948 1 T1 3172 T2 8 T3 20693
full_word 39657983 1 T1 2859 T2 3 T3 17487



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 79331501 1 T1 6031 T2 11 T3 38180
auto[TlIntgErrCmd] 144 1 T50 7 T51 6 T52 10
auto[TlIntgErrData] 148 1 T50 7 T51 8 T52 5
auto[TlIntgErrBoth] 138 1 T50 6 T51 6 T52 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31888462 1 T1 2505 T2 1 T3 15456
auto[1] 47443469 1 T1 3526 T2 10 T3 22724



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 16427539 1 T1 1205 T3 7715 T4 157
auto[TlIntgErrNone] partial auto[1] 23246010 1 T1 1967 T2 8 T3 12978
auto[TlIntgErrNone] full_word auto[0] 15460742 1 T1 1300 T2 1 T3 7741
auto[TlIntgErrNone] full_word auto[1] 24197210 1 T1 1559 T2 2 T3 9746
auto[TlIntgErrCmd] partial auto[0] 50 1 T51 3 T52 4 T122 2
auto[TlIntgErrCmd] partial auto[1] 87 1 T50 6 T51 3 T52 6
auto[TlIntgErrCmd] full_word auto[0] 5 1 T50 1 T123 1 T124 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T125 1 T126 1 - -
auto[TlIntgErrData] partial auto[0] 75 1 T50 3 T51 3 T52 3
auto[TlIntgErrData] partial auto[1] 56 1 T50 3 T51 3 T52 2
auto[TlIntgErrData] full_word auto[0] 4 1 T122 1 T123 1 T127 2
auto[TlIntgErrData] full_word auto[1] 13 1 T50 1 T51 2 T128 1
auto[TlIntgErrBoth] partial auto[0] 45 1 T50 2 T51 2 T52 1
auto[TlIntgErrBoth] partial auto[1] 86 1 T50 2 T51 3 T52 4
auto[TlIntgErrBoth] full_word auto[0] 2 1 T51 1 T129 1 - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T50 2 T123 1 T127 1

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