Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	424336228	947224	0	0
intr_enable_rd_A	424336228	2992	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424336228	947224	0	0
T11	0	66441	0	0
T12	0	104396	0	0
T13	0	228467	0	0
T14	0	62718	0	0
T15	0	138116	0	0
T26	758629	216427	0	0
T50	0	4	0	0
T54	0	2	0	0
T59	0	728	0	0
T60	0	1075	0	0
T61	887	0	0	0
T62	164150	0	0	0
T63	292281	0	0	0
T64	105440	0	0	0
T65	1357	0	0	0
T66	566154	0	0	0
T67	571042	0	0	0
T68	225668	0	0	0
T69	18906	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424336228	2992	0	0
T11	146383	0	0	0
T54	0	17	0	0
T56	0	22	0	0
T70	487123	86	0	0
T71	0	7	0	0
T72	0	2	0	0
T73	0	100	0	0
T74	0	36	0	0
T75	0	16	0	0
T76	0	39	0	0
T77	0	29	0	0
T78	48780	0	0	0
T79	299891	0	0	0
T80	816526	0	0	0
T81	27089	0	0	0
T82	31950	0	0	0
T83	1086	0	0	0
T84	25887	0	0	0
T85	22137	0	0	0