Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38468330

1

T1

24295

T2

43923

T3

410323

full_word

38097609

1

T1

20974

T2

36141

T3

454740

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76565559	1			T1	45269		T2	80064		T3	865063
auto[TlIntgErrCmd]	126	1			T52	7		T53	3		T54	6
auto[TlIntgErrData]	122	1			T52	6		T53	2		T54	7
auto[TlIntgErrBoth]	132	1			T52	7		T53	5		T54	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30635185

1

T1

18514

T2

32453

T3

336981

auto[1]

45930754

1

T1

26755

T2

47611

T3

528082

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15904682	1			T1	9396		T2	16653		T3	172480
auto[TlIntgErrNone]	partial	auto[1]	22563303	1			T1	14899		T2	27270		T3	237843
auto[TlIntgErrNone]	full_word	auto[0]	14730341	1			T1	9118		T2	15800		T3	164501
auto[TlIntgErrNone]	full_word	auto[1]	23367233	1			T1	11856		T2	20341		T3	290239
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T52	2		T54	2		T114	4
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T52	3		T53	3		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T54	1		T119	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	2		T121	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T52	2		T53	1		T54	5
auto[TlIntgErrData]	partial	auto[1]	58	1			T52	2		T53	1		T54	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T115	1		T122	1		T123	2
auto[TlIntgErrData]	full_word	auto[1]	9	1			T52	2		T114	2		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T52	4		T53	2		T54	3
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T52	2		T53	3		T54	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T115	2		T116	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T52	1		T114	1		T120	1