Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	97.23			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.31	100.00	97.23			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	97.23			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.23	94.86	97.60	100.00		98.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.83	95.83	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_size	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_key_length	100.00	100.00
u_cfg_key_swap	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_continue	100.00	100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_cmd_hash_stop	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_10	100.00	100.00
u_digest_11	100.00	100.00
u_digest_12	100.00	100.00
u_digest_13	100.00	100.00
u_digest_14	100.00	100.00
u_digest_15	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_digest_8	100.00	100.00
u_digest_9	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	62.59	77.78	50.00			60.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_10	50.00	50.00
u_key_11	50.00	50.00
u_key_12	50.00	50.00
u_key_13	50.00	50.00
u_key_14	50.00	50.00
u_key_15	50.00	50.00
u_key_16	50.00	50.00
u_key_17	50.00	50.00
u_key_18	50.00	50.00
u_key_19	50.00	50.00
u_key_2	100.00	100.00
u_key_20	50.00	50.00
u_key_21	50.00	50.00
u_key_22	50.00	50.00
u_key_23	50.00	50.00
u_key_24	50.00	50.00
u_key_25	50.00	50.00
u_key_26	50.00	50.00
u_key_27	50.00	50.00
u_key_28	50.00	50.00
u_key_29	50.00	50.00
u_key_3	100.00	100.00
u_key_30	50.00	50.00
u_key_31	50.00	50.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_key_8	50.00	50.00
u_key_9	50.00	50.00
u_msg_length_lower	100.00	100.00
u_msg_length_upper	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_hmac_idle	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		486	486	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	877	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	912	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	933	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	954	1	1	100.00
CONT_ASSIGN	961	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	1003	1	1	100.00
CONT_ASSIGN	1017	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00
CONT_ASSIGN	1080	1	1	100.00
CONT_ASSIGN	1087	1	1	100.00
CONT_ASSIGN	1101	1	1	100.00
CONT_ASSIGN	1108	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1129	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1164	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1192	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1213	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1234	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1444	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1465	1	1	100.00
CONT_ASSIGN	1479	1	1	100.00
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1507	1	1	100.00
CONT_ASSIGN	1521	1	1	100.00
CONT_ASSIGN	1528	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1591	1	1	100.00
CONT_ASSIGN	1605	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1647	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1675	1	1	100.00
CONT_ASSIGN	1689	1	1	100.00
CONT_ASSIGN	1696	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1717	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1738	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1759	1	1	100.00
CONT_ASSIGN	1773	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1822	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1857	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1878	1	1	100.00
CONT_ASSIGN	1885	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1919	1	1	100.00
CONT_ASSIGN	1925	1	1	100.00
CONT_ASSIGN	1939	1	1	100.00
ALWAYS	1945	60	60	100.00
CONT_ASSIGN	2007	1	1	100.00
ALWAYS	2011	1	1	100.00
CONT_ASSIGN	2074	1	1	100.00
CONT_ASSIGN	2076	1	1	100.00
CONT_ASSIGN	2078	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2083	1	1	100.00
CONT_ASSIGN	2085	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2090	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2093	1	1	100.00
CONT_ASSIGN	2095	1	1	100.00
CONT_ASSIGN	2096	1	1	100.00
CONT_ASSIGN	2097	1	1	100.00
CONT_ASSIGN	2099	1	1	100.00
CONT_ASSIGN	2101	1	1	100.00
CONT_ASSIGN	2103	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2122	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2131	1	1	100.00
CONT_ASSIGN	2133	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2167	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2170	1	1	100.00
CONT_ASSIGN	2172	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2175	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2190	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2193	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2203	1	1	100.00
CONT_ASSIGN	2205	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2211	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2222	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2225	1	1	100.00
CONT_ASSIGN	2226	1	1	100.00
CONT_ASSIGN	2228	1	1	100.00
CONT_ASSIGN	2229	1	1	100.00
CONT_ASSIGN	2230	1	1	100.00
CONT_ASSIGN	2232	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2234	1	1	100.00
CONT_ASSIGN	2236	1	1	100.00
CONT_ASSIGN	2237	1	1	100.00
CONT_ASSIGN	2238	1	1	100.00
CONT_ASSIGN	2240	1	1	100.00
CONT_ASSIGN	2241	1	1	100.00
CONT_ASSIGN	2242	1	1	100.00
CONT_ASSIGN	2244	1	1	100.00
CONT_ASSIGN	2245	1	1	100.00
CONT_ASSIGN	2246	1	1	100.00
CONT_ASSIGN	2248	1	1	100.00
CONT_ASSIGN	2249	1	1	100.00
CONT_ASSIGN	2250	1	1	100.00
CONT_ASSIGN	2252	1	1	100.00
CONT_ASSIGN	2253	1	1	100.00
CONT_ASSIGN	2254	1	1	100.00
CONT_ASSIGN	2256	1	1	100.00
CONT_ASSIGN	2257	1	1	100.00
CONT_ASSIGN	2258	1	1	100.00
CONT_ASSIGN	2260	1	1	100.00
CONT_ASSIGN	2261	1	1	100.00
CONT_ASSIGN	2262	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2265	1	1	100.00
CONT_ASSIGN	2266	1	1	100.00
CONT_ASSIGN	2268	1	1	100.00
CONT_ASSIGN	2269	1	1	100.00
CONT_ASSIGN	2270	1	1	100.00
CONT_ASSIGN	2272	1	1	100.00
CONT_ASSIGN	2273	1	1	100.00
CONT_ASSIGN	2274	1	1	100.00
CONT_ASSIGN	2276	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2278	1	1	100.00
CONT_ASSIGN	2280	1	1	100.00
CONT_ASSIGN	2281	1	1	100.00
CONT_ASSIGN	2282	1	1	100.00
CONT_ASSIGN	2284	1	1	100.00
CONT_ASSIGN	2285	1	1	100.00
CONT_ASSIGN	2286	1	1	100.00
CONT_ASSIGN	2288	1	1	100.00
CONT_ASSIGN	2289	1	1	100.00
CONT_ASSIGN	2290	1	1	100.00
CONT_ASSIGN	2292	1	1	100.00
ALWAYS	2296	60	60	100.00
ALWAYS	2360	79	79	100.00
CONT_ASSIGN	2627	0	0
CONT_ASSIGN	2635	1	1	100.00
CONT_ASSIGN	2636	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
528	1	1
543	1	1
559	1	1
575	1	1
581	1	1
595	1	1
601	1	1
616	1	1
632	1	1
648	1	1
664	1	1
680	1	1
696	1	1
712	1	1
718	1	1
733	1	1
749	1	1
765	1	1
781	1	1
877	1	1
891	1	1
898	1	1
912	1	1
919	1	1
933	1	1
940	1	1
954	1	1
961	1	1
975	1	1
982	1	1
996	1	1
1003	1	1
1017	1	1
1024	1	1
1038	1	1
1045	1	1
1059	1	1
1066	1	1
1080	1	1
1087	1	1
1101	1	1
1108	1	1
1122	1	1
1129	1	1
1143	1	1
1150	1	1
1164	1	1
1171	1	1
1185	1	1
1192	1	1
1206	1	1
1213	1	1
1227	1	1
1234	1	1
1248	1	1
1255	1	1
1269	1	1
1276	1	1
1290	1	1
1297	1	1
1311	1	1
1318	1	1
1332	1	1
1339	1	1
1353	1	1
1360	1	1
1374	1	1
1381	1	1
1395	1	1
1402	1	1
1416	1	1
1423	1	1
1437	1	1
1444	1	1
1458	1	1
1465	1	1
1479	1	1
1486	1	1
1500	1	1
1507	1	1
1521	1	1
1528	1	1
1542	1	1
1549	1	1
1563	1	1
1570	1	1
1584	1	1
1591	1	1
1605	1	1
1612	1	1
1626	1	1
1633	1	1
1647	1	1
1654	1	1
1668	1	1
1675	1	1
1689	1	1
1696	1	1
1710	1	1
1717	1	1
1731	1	1
1738	1	1
1752	1	1
1759	1	1
1773	1	1
1780	1	1
1794	1	1
1801	1	1
1815	1	1
1822	1	1
1836	1	1
1843	1	1
1857	1	1
1864	1	1
1878	1	1
1885	1	1
1899	1	1
1905	1	1
1919	1	1
1925	1	1
1939	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1961	1	1
1962	1	1
1963	1	1
1964	1	1
1965	1	1
1966	1	1
1967	1	1
1968	1	1
1969	1	1
1970	1	1
1971	1	1
1972	1	1
1973	1	1
1974	1	1
1975	1	1
1976	1	1
1977	1	1
1978	1	1
1979	1	1
1980	1	1
1981	1	1
1982	1	1
1983	1	1
1984	1	1
1985	1	1
1986	1	1
1987	1	1
1988	1	1
1989	1	1
1990	1	1
1991	1	1
1992	1	1
1993	1	1
1994	1	1
1995	1	1
1996	1	1
1997	1	1
1998	1	1
1999	1	1
2000	1	1
2001	1	1
2002	1	1
2003	1	1
2004	1	1
2007	1	1
2011	1	1
2074	1	1
2076	1	1
2078	1	1
2079	1	1
2081	1	1
2083	1	1
2085	1	1
2086	1	1
2088	1	1
2090	1	1
2092	1	1
2093	1	1
2095	1	1
2096	1	1
2097	1	1
2099	1	1
2101	1	1
2103	1	1
2105	1	1
2107	1	1
2109	1	1
2111	1	1
2112	1	1
2114	1	1
2116	1	1
2118	1	1
2120	1	1
2121	1	1
2122	1	1
2124	1	1
2125	1	1
2127	1	1
2128	1	1
2130	1	1
2131	1	1
2133	1	1
2134	1	1
2136	1	1
2137	1	1
2139	1	1
2140	1	1
2142	1	1
2143	1	1
2145	1	1
2146	1	1
2148	1	1
2149	1	1
2151	1	1
2152	1	1
2154	1	1
2155	1	1
2157	1	1
2158	1	1
2160	1	1
2161	1	1
2163	1	1
2164	1	1
2166	1	1
2167	1	1
2169	1	1
2170	1	1
2172	1	1
2173	1	1
2175	1	1
2176	1	1
2178	1	1
2179	1	1
2181	1	1
2182	1	1
2184	1	1
2185	1	1
2187	1	1
2188	1	1
2190	1	1
2191	1	1
2193	1	1
2194	1	1
2196	1	1
2197	1	1
2199	1	1
2200	1	1
2202	1	1
2203	1	1
2205	1	1
2206	1	1
2208	1	1
2209	1	1
2211	1	1
2212	1	1
2214	1	1
2215	1	1
2217	1	1
2218	1	1
2220	1	1
2221	1	1
2222	1	1
2224	1	1
2225	1	1
2226	1	1
2228	1	1
2229	1	1
2230	1	1
2232	1	1
2233	1	1
2234	1	1
2236	1	1
2237	1	1
2238	1	1
2240	1	1
2241	1	1
2242	1	1
2244	1	1
2245	1	1
2246	1	1
2248	1	1
2249	1	1
2250	1	1
2252	1	1
2253	1	1
2254	1	1
2256	1	1
2257	1	1
2258	1	1
2260	1	1
2261	1	1
2262	1	1
2264	1	1
2265	1	1
2266	1	1
2268	1	1
2269	1	1
2270	1	1
2272	1	1
2273	1	1
2274	1	1
2276	1	1
2277	1	1
2278	1	1
2280	1	1
2281	1	1
2282	1	1
2284	1	1
2285	1	1
2286	1	1
2288	1	1
2289	1	1
2290	1	1
2292	1	1
2296	1	1
2297	1	1
2298	1	1
2299	1	1
2300	1	1
2301	1	1
2302	1	1
2303	1	1
2304	1	1
2305	1	1
2306	1	1
2307	1	1
2308	1	1
2309	1	1
2310	1	1
2311	1	1
2312	1	1
2313	1	1
2314	1	1
2315	1	1
2316	1	1
2317	1	1
2318	1	1
2319	1	1
2320	1	1
2321	1	1
2322	1	1
2323	1	1
2324	1	1
2325	1	1
2326	1	1
2327	1	1
2328	1	1
2329	1	1
2330	1	1
2331	1	1
2332	1	1
2333	1	1
2334	1	1
2335	1	1
2336	1	1
2337	1	1
2338	1	1
2339	1	1
2340	1	1
2341	1	1
2342	1	1
2343	1	1
2344	1	1
2345	1	1
2346	1	1
2347	1	1
2348	1	1
2349	1	1
2350	1	1
2351	1	1
2352	1	1
2353	1	1
2354	1	1
2355	1	1
2360	1	1
2361	1	1
2363	1	1
2364	1	1
2365	1	1
2369	1	1
2370	1	1
2371	1	1
2375	1	1
2376	1	1
2377	1	1
2381	1	1
2385	1	1
2386	1	1
2387	1	1
2388	1	1
2389	1	1
2390	1	1
2391	1	1
2395	1	1
2396	1	1
2397	1	1
2398	1	1
2402	1	1
2403	1	1
2404	1	1
2405	1	1
2409	1	1
2413	1	1
2417	1	1
2421	1	1
2425	1	1
2429	1	1
2433	1	1
2437	1	1
2441	1	1
2445	1	1
2449	1	1
2453	1	1
2457	1	1
2461	1	1
2465	1	1
2469	1	1
2473	1	1
2477	1	1
2481	1	1
2485	1	1
2489	1	1
2493	1	1
2497	1	1
2501	1	1
2505	1	1
2509	1	1
2513	1	1
2517	1	1
2521	1	1
2525	1	1
2529	1	1
2533	1	1
2537	1	1
2541	1	1
2545	1	1
2549	1	1
2553	1	1
2557	1	1
2561	1	1
2565	1	1
2569	1	1
2573	1	1
2577	1	1
2581	1	1
2585	1	1
2589	1	1
2593	1	1
2597	1	1
2601	1	1
2605	1	1
2609	1	1
2613	1	1
2627		unreachable
2635	1	1
2636	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	687	668	97.23
Logical	687	668	97.23
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-2128	99.53
2131-2290	93.56

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		69	69	100.00
TERNARY	2007	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	2361	60	60	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2007	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[4096:8191]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T52,T53,T54
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2361	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	410966614	52605698	0	0
reAfterRv	410966614	52605698	0	0
rePulse	410966614	29554693	0	0
wePulse	410966614	23051005	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	52605698	0	0
T1	128097	28284	0	0
T2	165990	48827	0	0
T3	607636	591385	0	0
T4	667763	39852	0	0
T8	522943	31498	0	0
T9	329466	23819	0	0
T13	24733	6069	0	0
T16	1178	16	0	0
T21	37845	10937	0	0
T23	167704	49726	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	52605698	0	0
T1	128097	28284	0	0
T2	165990	48827	0	0
T3	607636	591385	0	0
T4	667763	39852	0	0
T8	522943	31498	0	0
T9	329466	23819	0	0
T13	24733	6069	0	0
T16	1178	16	0	0
T21	37845	10937	0	0
T23	167704	49726	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	29554693	0	0
T1	128097	18514	0	0
T2	165990	32453	0	0
T3	607636	336981	0	0
T4	667763	26174	0	0
T8	522943	20681	0	0
T9	329466	14421	0	0
T13	24733	4916	0	0
T16	1178	1	0	0
T21	37845	7148	0	0
T23	167704	32666	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	23051005	0	0
T1	128097	9770	0	0
T2	165990	16374	0	0
T3	607636	254404	0	0
T4	667763	13678	0	0
T8	522943	10817	0	0
T9	329466	9398	0	0
T13	24733	1153	0	0
T16	1178	15	0	0
T21	37845	3789	0	0
T23	167704	17060	0	0