Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.83	95.83	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	410966614	1380333	0	0
intr_enable_rd_A	410966614	4502	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	1380333	0	0
T5	100446	427213	0	0
T6	0	100730	0	0
T7	0	68654	0	0
T39	0	225010	0	0
T40	0	79512	0	0
T55	0	16	0	0
T59	0	85214	0	0
T60	0	496	0	0
T61	0	6	0	0
T62	0	190	0	0
T63	396130	0	0	0
T64	271528	0	0	0
T65	150790	0	0	0
T66	15016	0	0	0
T67	329869	0	0	0
T68	41157	0	0	0
T69	365766	0	0	0
T70	2956	0	0	0
T71	1393	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410966614	4502	0	0
T10	104549	0	0	0
T11	55983	0	0	0
T20	110988	75	0	0
T49	208859	0	0	0
T50	53479	0	0	0
T51	1036	0	0	0
T55	0	22	0	0
T72	0	15	0	0
T73	0	31	0	0
T74	0	66	0	0
T75	0	23	0	0
T76	0	27	0	0
T77	0	19	0	0
T78	0	12	0	0
T79	0	24	0	0
T80	5894	0	0	0
T81	4549	0	0	0
T82	633184	0	0	0
T83	246568	0	0	0