Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35457080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37325687

1

T1

182

T2

288

T3

163508

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29289673	1			T1	197		T2	293		T3	134765
values[0x0]	20216571	1			T1	76		T2	132		T3	90571
values[0x1]	23276523	1			T1	104		T2	132		T3	103527

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26268939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46513828

1

T1

237

T2

347

T3

204946

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	334919	1			T3	271		T4	36		T5	3
valid_sources[0x01]	251258	1			T2	2		T3	661		T4	50
valid_sources[0x02]	263821	1			T2	3		T3	468		T4	58
valid_sources[0x03]	281970	1			T2	3		T3	549		T4	44
valid_sources[0x04]	373810	1			T2	1		T3	475		T4	54
valid_sources[0x05]	263637	1			T2	2		T3	1049		T4	46
valid_sources[0x06]	268295	1			T2	3		T3	477		T4	32
valid_sources[0x07]	284439	1			T2	1		T3	570		T4	47
valid_sources[0x08]	280150	1			T2	3		T3	439		T4	45
valid_sources[0x09]	262939	1			T2	3		T3	546		T4	36
valid_sources[0x0a]	249901	1			T2	2		T3	341		T4	53
valid_sources[0x0b]	251889	1			T2	1		T3	554		T4	32
valid_sources[0x0c]	294795	1			T2	6		T3	422		T4	49
valid_sources[0x0d]	344870	1			T1	234		T2	2		T3	412
valid_sources[0x0e]	375868	1			T2	2		T3	431		T4	40
valid_sources[0x0f]	245898	1			T3	394		T4	41		T5	52
valid_sources[0x10]	319470	1			T2	6		T3	5521		T4	65
valid_sources[0x11]	251769	1			T2	2		T3	518		T4	50
valid_sources[0x12]	277542	1			T2	4		T3	428		T4	45
valid_sources[0x13]	271233	1			T2	4		T3	371		T4	48
valid_sources[0x14]	283473	1			T3	508		T4	43		T5	49
valid_sources[0x15]	281629	1			T2	5		T3	694		T4	66
valid_sources[0x16]	269841	1			T2	4		T3	498		T4	65
valid_sources[0x17]	285172	1			T2	1		T3	423		T4	50
valid_sources[0x18]	279140	1			T2	6		T3	487		T4	58
valid_sources[0x19]	249766	1			T2	3		T3	624		T4	33
valid_sources[0x1a]	249212	1			T2	1		T3	565		T4	25
valid_sources[0x1b]	308883	1			T2	2		T3	17057		T4	38
valid_sources[0x1c]	308182	1			T3	473		T4	49		T5	179
valid_sources[0x1d]	249151	1			T2	3		T3	2550		T4	50
valid_sources[0x1e]	380195	1			T2	2		T3	477		T4	46
valid_sources[0x1f]	315484	1			T2	2		T3	468		T4	27
valid_sources[0x20]	271199	1			T2	1		T3	578		T4	53
valid_sources[0x21]	261077	1			T3	448		T4	53		T5	14
valid_sources[0x22]	325520	1			T2	2		T3	374		T4	42
valid_sources[0x23]	318928	1			T2	2		T3	380		T4	38
valid_sources[0x24]	305227	1			T2	5		T3	449		T4	54
valid_sources[0x25]	275453	1			T2	1		T3	366		T4	44
valid_sources[0x26]	244910	1			T2	3		T3	485		T4	37
valid_sources[0x27]	240572	1			T2	6		T3	408		T4	41
valid_sources[0x28]	284385	1			T2	2		T3	533		T4	51
valid_sources[0x29]	282087	1			T2	1		T3	682		T4	56
valid_sources[0x2a]	284260	1			T2	1		T3	515		T4	41
valid_sources[0x2b]	298834	1			T2	2		T3	586		T4	61
valid_sources[0x2c]	275244	1			T2	3		T3	835		T4	60
valid_sources[0x2d]	301800	1			T2	2		T3	567		T4	39
valid_sources[0x2e]	262259	1			T2	4		T3	370		T4	32
valid_sources[0x2f]	283498	1			T2	1		T3	446		T4	38
valid_sources[0x30]	292228	1			T2	4		T3	524		T4	43
valid_sources[0x31]	237604	1			T2	1		T3	346		T4	60
valid_sources[0x32]	246668	1			T2	4		T3	532		T4	34
valid_sources[0x33]	369406	1			T3	432		T4	33		T5	48
valid_sources[0x34]	272736	1			T2	3		T3	680		T4	37
valid_sources[0x35]	277420	1			T2	1		T3	391		T4	33
valid_sources[0x36]	264733	1			T2	4		T3	1116		T4	25
valid_sources[0x37]	246841	1			T2	3		T3	4836		T4	41
valid_sources[0x38]	277477	1			T2	4		T3	475		T4	48
valid_sources[0x39]	331665	1			T2	1		T3	569		T4	39
valid_sources[0x3a]	252434	1			T2	2		T3	368		T4	48
valid_sources[0x3b]	247918	1			T2	2		T3	310		T4	56
valid_sources[0x3c]	279204	1			T2	2		T3	541		T4	41
valid_sources[0x3d]	261608	1			T2	3		T3	354		T4	36
valid_sources[0x3e]	342808	1			T3	416		T4	53		T5	35
valid_sources[0x3f]	245055	1			T3	5390		T4	29		T5	57
valid_sources[0x40]	327517	1			T2	2		T3	376		T4	49
valid_sources[0x41]	330836	1			T2	2		T3	463		T4	33
valid_sources[0x42]	302253	1			T2	4		T3	496		T4	58
valid_sources[0x43]	237516	1			T2	2		T3	513		T4	30
valid_sources[0x44]	246707	1			T2	5		T3	453		T4	27
valid_sources[0x45]	236188	1			T3	300		T4	40		T5	43
valid_sources[0x46]	258027	1			T2	4		T3	369		T4	41
valid_sources[0x47]	283537	1			T2	2		T3	516		T4	28
valid_sources[0x48]	302172	1			T2	2		T3	349		T4	35
valid_sources[0x49]	314280	1			T2	2		T3	566		T4	31
valid_sources[0x4a]	297651	1			T2	1		T3	417		T4	43
valid_sources[0x4b]	337181	1			T2	3		T3	263		T4	50
valid_sources[0x4c]	242827	1			T2	1		T3	491		T4	45
valid_sources[0x4d]	303318	1			T2	5		T3	384		T4	28
valid_sources[0x4e]	296255	1			T2	1		T3	541		T4	55
valid_sources[0x4f]	271737	1			T2	5		T3	419		T4	32
valid_sources[0x50]	249972	1			T2	6		T3	746		T4	40
valid_sources[0x51]	260137	1			T2	1		T3	435		T4	45
valid_sources[0x52]	322379	1			T2	1		T3	576		T4	48
valid_sources[0x53]	316814	1			T2	3		T3	7835		T4	46
valid_sources[0x54]	252047	1			T2	3		T3	337		T4	51
valid_sources[0x55]	275142	1			T2	4		T3	299		T4	41
valid_sources[0x56]	274103	1			T2	4		T3	245		T4	49
valid_sources[0x57]	267471	1			T2	1		T3	483		T4	48
valid_sources[0x58]	257983	1			T2	4		T3	390		T4	43
valid_sources[0x59]	394685	1			T2	1		T3	411		T4	40
valid_sources[0x5a]	268686	1			T2	1		T3	428		T4	54
valid_sources[0x5b]	261545	1			T3	317		T4	56		T5	40
valid_sources[0x5c]	257237	1			T2	1		T3	555		T4	43
valid_sources[0x5d]	373271	1			T2	1		T3	406		T4	49
valid_sources[0x5e]	292752	1			T1	1		T2	3		T3	583
valid_sources[0x5f]	312923	1			T2	3		T3	941		T4	32
valid_sources[0x60]	260353	1			T2	2		T3	488		T4	35
valid_sources[0x61]	297708	1			T2	5		T3	563		T4	42
valid_sources[0x62]	270164	1			T3	418		T4	59		T5	45
valid_sources[0x63]	249183	1			T2	3		T3	541		T4	38
valid_sources[0x64]	260942	1			T2	2		T3	556		T4	64
valid_sources[0x65]	300406	1			T2	1		T3	452		T4	40
valid_sources[0x66]	315454	1			T2	2		T3	525		T4	58
valid_sources[0x67]	246397	1			T3	695		T4	36		T5	55
valid_sources[0x68]	351734	1			T2	3		T3	485		T4	40
valid_sources[0x69]	319831	1			T3	358		T4	52		T5	139
valid_sources[0x6a]	281412	1			T2	1		T3	1030		T4	49
valid_sources[0x6b]	301344	1			T2	2		T3	528		T4	39
valid_sources[0x6c]	248556	1			T3	449		T4	53		T5	47
valid_sources[0x6d]	239663	1			T2	3		T3	287		T4	51
valid_sources[0x6e]	274967	1			T2	3		T3	352		T4	40
valid_sources[0x6f]	273868	1			T2	3		T3	397		T4	44
valid_sources[0x70]	287031	1			T2	2		T3	551		T4	48
valid_sources[0x71]	285070	1			T2	1		T3	504		T4	65
valid_sources[0x72]	275015	1			T2	1		T3	17385		T4	58
valid_sources[0x73]	402930	1			T2	1		T3	555		T4	34
valid_sources[0x74]	375939	1			T1	135		T3	465		T4	52
valid_sources[0x75]	285169	1			T2	2		T3	527		T4	45
valid_sources[0x76]	279292	1			T3	366		T4	79		T5	233
valid_sources[0x77]	254589	1			T1	2		T2	1		T3	560
valid_sources[0x78]	262748	1			T2	1		T3	463		T4	45
valid_sources[0x79]	324603	1			T2	1		T3	382		T4	45
valid_sources[0x7a]	259271	1			T2	1		T3	517		T4	51
valid_sources[0x7b]	282877	1			T2	1		T3	593		T4	30
valid_sources[0x7c]	255989	1			T2	3		T3	521		T4	64
valid_sources[0x7d]	282426	1			T2	2		T3	558		T4	46
valid_sources[0x7e]	240778	1			T2	5		T3	412		T4	60
valid_sources[0x7f]	261502	1			T2	4		T3	1025		T4	35
valid_sources[0x80]	253256	1			T2	2		T3	492		T4	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14416806

1

T1

93

T2

127

T3

67461

values[0x0]

all_enables

biggest_size

12082828

1

T1

45

T2

81

T3

51243

values[0x1]

all_enables

biggest_size

10826053

1

T1

44

T2

80

T3

44804