Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38562100

1

T1

195

T2

269

T3

165355

full_word

37527495

1

T1

182

T2

288

T3

163508

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76089175	1			T1	377		T2	557		T3	328863
auto[TlIntgErrCmd]	134	1			T49	7		T50	2		T51	10
auto[TlIntgErrData]	144	1			T49	19		T50	4		T51	9
auto[TlIntgErrBoth]	142	1			T49	4		T50	4		T51	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30330376

1

T1

197

T2

293

T3

134765

auto[1]

45759219

1

T1

180

T2

264

T3

194098

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15834095	1			T1	104		T2	166		T3	67304
auto[TlIntgErrNone]	partial	auto[1]	22727619	1			T1	91		T2	103		T3	98051
auto[TlIntgErrNone]	full_word	auto[0]	14496086	1			T1	93		T2	127		T3	67461
auto[TlIntgErrNone]	full_word	auto[1]	23031375	1			T1	89		T2	161		T3	96047
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T49	3		T50	2		T51	4
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T49	3		T51	6		T109	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T108	1		T111	1		T110	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T49	1		T108	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	74	1			T49	14		T50	1		T51	4
auto[TlIntgErrData]	partial	auto[1]	61	1			T49	3		T50	3		T51	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T49	2		T51	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T111	1		T110	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T49	1		T50	3		T51	6
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T49	2		T50	1		T51	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T49	1		T51	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T114	1		T107	1		T112	1