Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.83	95.83	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	414297812	1778134	0	0
intr_enable_rd_A	414297812	2849	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414297812	1778134	0	0
T9	0	67820	0	0
T10	0	24045	0	0
T11	0	400126	0	0
T12	0	25167	0	0
T13	0	1888	0	0
T19	150296	65277	0	0
T24	272669	0	0	0
T25	0	103618	0	0
T49	0	6	0	0
T50	0	3	0	0
T54	0	5	0	0
T55	38641	0	0	0
T56	215538	0	0	0
T57	5198	0	0	0
T58	2897	0	0	0
T59	4117	0	0	0
T60	560628	0	0	0
T61	200404	0	0	0
T62	91681	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414297812	2849	0	0
T27	3317	0	0	0
T32	257397	0	0	0
T36	0	55	0	0
T63	239963	4	0	0
T64	0	39	0	0
T65	0	24	0	0
T66	0	1	0	0
T67	0	44	0	0
T68	0	20	0	0
T69	0	40	0	0
T70	0	50	0	0
T71	0	332	0	0
T72	300914	0	0	0
T73	294209	0	0	0
T74	2966	0	0	0
T75	119769	0	0	0
T76	271050	0	0	0
T77	420432	0	0	0
T78	3967	0	0	0