Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.24	93.29	87.26		88.89	83.52

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	88.24	93.29	87.26		88.89	83.52

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.24	93.29	87.26		88.89	83.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.24	93.29	87.26		88.89	83.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.83	95.83	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		164	153	93.29
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	136	21	21	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	211	16	15	93.75
CONT_ASSIGN	235	1	1	100.00
ALWAYS	238	4	4	100.00
CONT_ASSIGN	246	1	1	100.00
ALWAYS	254	10	6	60.00
ALWAYS	272	3	3	100.00
ALWAYS	278	6	6	100.00
ALWAYS	288	4	4	100.00
ALWAYS	296	6	6	100.00
CONT_ASSIGN	305	1	1	100.00
ALWAYS	308	3	3	100.00
ALWAYS	313	70	64	91.43
CONT_ASSIGN	453	1	1	100.00
ALWAYS	458	3	3	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	480	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
125	1	1
126	1	1
128	1	1
129	1	1
131	1	1
132	1	1
136	1	1
138	1	1
140	1	1
142	1	1
144	1	1
148	1	1
150	1	1
152	1	1
154	1	1
158	1	1
160	1	1
162	1	1
164	1	1
168	1	1
169	1	1
171	1	1
172	1	1
177	1	1
178	1	1
180	1	1
181	1	1
192	1	1
194	1	1
195	1	1
211	1	1
212	1	1
213	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
222	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			==> MISSING_ELSE
232	0	1
235	1	1
238	1	1
239	1	1
240	1	1
241	1	1
246	1	1
254	1	1
255	1	1
256	1	1
257	1	1
260	0	1
261	0	1
262	0	1
263	0	1
266	1	1
267	1	1
			MISSING_ELSE
272	2	2
273	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
			MISSING_ELSE
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
			==> MISSING_ELSE
305	1	1
308	2	2
309	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
332	1	1
333	1	1
334	1	1
335	1	1
337	1	1
338	1	1
339	1	1
340	0	1
342	0	1
343	0	1
345	1	1
350	1	1
352	1	1
353	1	1
355	1	1
357	1	1
359	1	1
364	1	1
365	1	1
367	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	0	1
375	0	1
377	1	1
378	1	1
383	1	1
385	1	1
386	1	1
387	1	1
389	1	1
390	0	1
392	1	1
396	1	1
401	1	1
402	1	1
403	1	1
404	1	1
406	1	1
410	1	1
412	1	1
413	1	1
414	1	1
415	1	1
417	1	1
423	1	1
424	1	1
426	1	1
427	1	1
429	1	1
431	1	1
433	1	1
439	1	1
441	1	1
453	1	1
458	1	1
459	1	1
461	1	1
466	1	1
477	1	1
480	1	1
481	1	1
483	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	212	185	87.26
Logical	212	185	87.26
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       128
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       128
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       129
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       194
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T5
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T5
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T17,T6

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T17,T6

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T5
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T5
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T17,T6

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T17,T6

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       217
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T5
1	Covered	T1,T2,T4

 LINE       219
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T17,T6

 LINE       219
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T17,T6

 LINE       219
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T5
1	Covered	T5,T6,T7

 LINE       222
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       224
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T4

 LINE       226
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T6,T7

 LINE       228
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T6,T7

 LINE       239
 EXPRESSION ((txcount[(BlockSizeBitsSHA256 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA256 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T17,T6
1	1	Covered	T4,T6,T7

 LINE       240
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T17,T6

 LINE       240
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T17,T6
1	Covered	T4,T6,T7

 LINE       241
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T17,T5,T6
1	1	Covered	T5,T6,T7

 LINE       241
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T17,T5,T6

 LINE       241
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T17,T5,T6
1	Covered	T5,T6,T7

 LINE       246
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T4

 LINE       300
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       305
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       305
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       339
 EXPRESSION (hmac_en_i && reg_hash_continue_i)
             ----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       365
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       372
 EXPRESSION (txcnt_eq_blksz && reg_hash_stop_q && (round_q == Inner))
             -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       372
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       386
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       406
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T7
0	1	0	Covered	T5,T6,T7
1	0	0	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T5,T6,T7

 LINE       406
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       406
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       406
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T4,T6,T7

 LINE       406
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       406
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T7

 LINE       453
 EXPRESSION ((reg_hash_stop_i == 1'b1) ? 1'b1 : (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       453
 SUB-EXPRESSION (reg_hash_stop_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       453
 SUB-EXPRESSION (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       453
 SUB-EXPRESSION ((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       453
 SUB-EXPRESSION (sha_hash_done_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       453
 SUB-EXPRESSION (reg_hash_stop_q == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       466
 EXPRESSION ((reg_hash_start_i || reg_hash_continue_i) ? 1'b0 : ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       466
 SUB-EXPRESSION (txcnt_eq_blksz && reg_hash_stop_d)
                 -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Not Covered

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	9	8	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	387	Covered	T1,T2,T4
StIPad	335	Covered	T1,T2,T4
StIdle	345	Covered	T1,T2,T3
StMsg	340	Covered	T1,T2,T4
StOPad	410	Covered	T1,T2,T4
StPushToMsgFifo	392	Covered	T1,T2,T4
StWaitResp	369	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	439	Covered	T1,T2,T4
StIPad->StMsg	353	Covered	T1,T2,T4
StIdle->StIPad	335	Covered	T1,T2,T4
StIdle->StMsg	340	Not Covered
StMsg->StWaitResp	369	Covered	T1,T2,T4
StOPad->StMsg	427	Covered	T1,T2,T4
StPushToMsgFifo->StOPad	410	Covered	T1,T2,T4
StWaitResp->StDone	387	Covered	T1,T2,T4
StWaitResp->StPushToMsgFifo	392	Covered	T1,T2,T4

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		91	76	83.52
TERNARY	125	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	129	2	2	100.00
TERNARY	192	2	2	100.00
TERNARY	194	2	2	100.00
TERNARY	195	7	6	85.71
TERNARY	305	2	2	100.00
TERNARY	453	3	1	33.33
TERNARY	466	4	3	75.00
CASE	136	6	6	100.00
IF	212	9	7	77.78
CASE	238	4	4	100.00
IF	255	7	3	42.86
IF	272	2	2	100.00
IF	278	4	4	100.00
IF	288	3	3	100.00
IF	296	4	3	75.00
IF	308	2	2	100.00
CASE	327	18	14	77.78
IF	458	2	2	100.00
IF	480	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	((!hmac_en_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	195	((!hmac_en_i)) ? 
-2-:	195	(((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? 
-3-:	195	(((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-4-:	195	(((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? 
-5-:	195	(((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-6-:	195	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	-	Covered	T4,T5,T6
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	1	-	Covered	T4,T5,T6
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	305	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	453	((reg_hash_stop_i == 1'b1)) ? 
-2-:	453	(((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	466	((reg_hash_start_i || reg_hash_continue_i)) ? 
-2-:	466	((st_q == StIdle)) ? 
-3-:	466	((txcnt_eq_blksz && reg_hash_stop_d)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	136	case (key_length_i)

Branches:

-1-	Status	Tests
Key_128	Covered	T4,T17,T6
Key_256	Covered	T1,T2,T3
Key_384	Covered	T4,T17,T5
Key_512	Covered	T5,T6,T7
Key_1024	Covered	T4,T17,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	if ((!hmac_en_i))
-2-:	216	if ((sel_msglen == SelIPadMsg))
-3-:	217	if ((digest_size_i == SHA2_256))
-4-:	219	if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
-5-:	222	if ((sel_msglen == SelOPadMsg))
-6-:	224	if ((digest_size_i == SHA2_256))
-7-:	226	if ((digest_size_i == SHA2_384))
-8-:	228	if ((digest_size_i == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T2,T4
0	1	0	1	-	-	-	-	Covered	T4,T17,T5
0	1	0	0	-	-	-	-	Covered	T5,T6,T7
0	0	-	-	1	1	-	-	Covered	T1,T2,T4
0	0	-	-	1	0	1	-	Covered	T4,T6,T7
0	0	-	-	1	0	0	1	Covered	T5,T6,T7
0	0	-	-	1	0	0	0	Not Covered
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	238	case (digest_size_i)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T4,T17,T6
SHA2_512	Covered	T17,T5,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	if (clr_txcount)
-2-:	257	if (load_txcount)
-3-:	260	case (digest_size_i)
-4-:	266	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	SHA2_256	-	Not Covered
0	1	SHA2_384	-	Not Covered
0	1	SHA2_512	-	Not Covered
0	1	default	-	Not Covered
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))
-2-:	280	if (reg_hash_process_i)
-3-:	282	if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))
-2-:	290	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	296	if ((!rst_ni))
-2-:	298	if (clr_fifo_wdata_sel)
-3-:	300	if ((fifo_wsel_o && fifo_wvalid_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	308	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	case (st_q)
-2-:	334	if ((hmac_en_i && reg_hash_start_i))
-3-:	339	if ((hmac_en_i && reg_hash_continue_i))
-4-:	352	if (txcnt_eq_blksz)
-5-:	367	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o)))
-6-:	372	if (((txcnt_eq_blksz && reg_hash_stop_q) && (round_q == Inner)))
-7-:	385	if (sha_hash_done_i)
-8-:	386	if ((round_q == Outer))
-9-:	389	if (reg_hash_stop_q)
-10-:	406	if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))))
-11-:	426	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIPad	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	0	1	-	-	-	-	-	Not Covered
StMsg	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	0	1	-	-	Not Covered
StWaitResp	-	-	-	-	-	1	0	0	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
StDone	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	458	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3