Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45108597

1

T1

30716

T2

3507

T3

2717

full_word

43654387

1

T1

25500

T2

25118

T3

2219

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88762604	1			T1	56216		T2	28625		T3	4936
auto[TlIntgErrCmd]	135	1			T47	7		T48	3		T49	8
auto[TlIntgErrData]	124	1			T47	8		T48	5		T49	5
auto[TlIntgErrBoth]	121	1			T47	5		T48	2		T49	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35108015

1

T1

22976

T2

1433

T3

2018

auto[1]

53654969

1

T1

33240

T2

27192

T3

2918

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18412116	1			T1	11813		T2	857		T3	1012
auto[TlIntgErrNone]	partial	auto[1]	26696133	1			T1	18903		T2	2650		T3	1705
auto[TlIntgErrNone]	full_word	auto[0]	16695721	1			T1	11163		T2	576		T3	1006
auto[TlIntgErrNone]	full_word	auto[1]	26958634	1			T1	14337		T2	24542		T3	1213
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T47	3		T48	3		T49	5
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T47	4		T49	3		T116	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T117	1		T118	1		T119	3
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T117	1		T120	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T47	4		T48	2		T49	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T47	3		T48	3		T49	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T47	1		T122	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T117	1		T118	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T47	1		T49	3		T116	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T47	4		T48	2		T49	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	1		T54	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T119	2		T125	1		T126	1