Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.83	95.83	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	513409564	2491646	0	0
intr_enable_rd_A	513409564	1923	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513409564	2491646	0	0
T8	439528	197173	0	0
T9	0	97829	0	0
T10	0	341138	0	0
T11	0	121638	0	0
T12	0	91404	0	0
T13	0	83522	0	0
T14	0	81194	0	0
T22	916	0	0	0
T24	347938	150894	0	0
T56	0	220788	0	0
T57	0	79363	0	0
T58	817274	0	0	0
T59	9509	0	0	0
T60	102073	0	0	0
T61	73417	0	0	0
T62	57494	0	0	0
T63	988	0	0	0
T64	254467	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513409564	1923	0	0
T23	132316	12	0	0
T26	79238	0	0	0
T50	0	61	0	0
T65	0	2	0	0
T66	0	51	0	0
T67	0	26	0	0
T68	0	25	0	0
T69	0	22	0	0
T70	0	53	0	0
T71	0	48	0	0
T72	0	9	0	0
T73	22767	0	0	0
T74	206235	0	0	0
T75	548353	0	0	0
T76	130178	0	0	0
T77	177252	0	0	0
T78	430737	0	0	0
T79	164245	0	0	0
T80	99094	0	0	0