Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43313658

1

T1

293

T2

179181

T3

1740

full_word

42335881

1

T1

310

T2

182211

T3

2764

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85649089	1			T1	603		T2	361392		T3	4504
auto[TlIntgErrCmd]	155	1			T51	6		T52	8		T53	3
auto[TlIntgErrData]	153	1			T51	13		T52	8		T53	3
auto[TlIntgErrBoth]	142	1			T51	11		T52	4		T53	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34317826

1

T1

309

T2

149055

T3

2325

auto[1]

51331713

1

T1

294

T2

212337

T3

2179

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17886854	1			T1	165		T2	74813		T3	1277
auto[TlIntgErrNone]	partial	auto[1]	25426388	1			T1	128		T2	104368		T3	463
auto[TlIntgErrNone]	full_word	auto[0]	16430773	1			T1	144		T2	74242		T3	1048
auto[TlIntgErrNone]	full_word	auto[1]	25905074	1			T1	166		T2	107969		T3	1716
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T52	6		T111	2		T115	1
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T51	6		T52	1		T53	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T52	1		T116	2		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T115	1		T118	2		T119	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T51	6		T52	3		T53	1
auto[TlIntgErrData]	partial	auto[1]	69	1			T51	5		T52	3		T53	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T51	1		T52	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T51	1		T52	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T51	4		T53	2		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T51	7		T52	4		T53	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T114	1		T120	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T53	1		T122	1		T123	1