Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.84	95.88	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	443114881	1798580	0	0
intr_enable_rd_A	443114881	2545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	1798580	0	0
T9	0	355319	0	0
T10	0	134690	0	0
T11	0	85912	0	0
T24	200186	92018	0	0
T27	0	64393	0	0
T28	0	47510	0	0
T45	0	236949	0	0
T57	0	98033	0	0
T58	0	11620	0	0
T59	0	213652	0	0
T60	102736	0	0	0
T61	35934	0	0	0
T62	275694	0	0	0
T63	3195	0	0	0
T64	30836	0	0	0
T65	751572	0	0	0
T66	406881	0	0	0
T67	54890	0	0	0
T68	13395	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	2545	0	0
T39	118485	10	0	0
T40	10155	0	0	0
T41	85406	0	0	0
T42	59602	0	0	0
T43	356621	0	0	0
T44	124712	0	0	0
T52	0	69	0	0
T54	0	28	0	0
T69	0	30	0	0
T70	0	44	0	0
T71	0	14	0	0
T72	0	54	0	0
T73	0	35	0	0
T74	0	25	0	0
T75	0	37	0	0
T76	783973	0	0	0
T77	6297	0	0	0
T78	510351	0	0	0
T79	218782	0	0	0