Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40453555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42200153

1

T1

22126

T2

27755

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33332294	1			T1	1666		T2	2534		T3	1
values[0x0]	22915711	1			T1	11426		T2	14448		T4	34285
values[0x1]	26405703	1			T1	12271		T2	15273		T4	39506

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30013617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52640091

1

T1

23367

T2

29485

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	391827	1			T1	49		T4	519		T5	139
valid_sources[0x01]	326464	1			T1	76		T4	525		T5	104
valid_sources[0x02]	375254	1			T1	64		T4	535		T5	115
valid_sources[0x03]	357261	1			T1	135		T4	532		T5	80
valid_sources[0x04]	270929	1			T1	43		T4	527		T5	113
valid_sources[0x05]	335639	1			T1	125		T4	527		T5	97
valid_sources[0x06]	289364	1			T1	68		T4	528		T5	118
valid_sources[0x07]	285907	1			T1	30		T4	558		T5	118
valid_sources[0x08]	314003	1			T1	152		T4	518		T5	125
valid_sources[0x09]	294071	1			T1	92		T3	1		T4	583
valid_sources[0x0a]	322148	1			T1	109		T4	571		T5	87
valid_sources[0x0b]	284888	1			T1	71		T4	502		T5	115
valid_sources[0x0c]	326297	1			T1	57		T4	564		T5	122
valid_sources[0x0d]	330738	1			T1	116		T4	518		T5	159
valid_sources[0x0e]	320261	1			T1	85		T4	534		T5	120
valid_sources[0x0f]	316281	1			T1	89		T4	485		T5	123
valid_sources[0x10]	272531	1			T1	142		T4	549		T5	102
valid_sources[0x11]	371546	1			T1	79		T4	507		T5	101
valid_sources[0x12]	345608	1			T1	149		T4	508		T5	95
valid_sources[0x13]	314440	1			T1	83		T4	524		T5	99
valid_sources[0x14]	306653	1			T1	63		T4	516		T5	110
valid_sources[0x15]	328324	1			T1	196		T4	551		T5	125
valid_sources[0x16]	295261	1			T1	38		T4	497		T5	119
valid_sources[0x17]	309732	1			T1	31		T4	559		T5	113
valid_sources[0x18]	310030	1			T1	7		T4	504		T5	97
valid_sources[0x19]	368638	1			T1	110		T4	502		T5	101
valid_sources[0x1a]	341682	1			T1	159		T4	484		T5	121
valid_sources[0x1b]	307144	1			T1	103		T4	539		T5	106
valid_sources[0x1c]	289305	1			T1	37		T4	537		T5	109
valid_sources[0x1d]	284358	1			T1	224		T4	538		T5	113
valid_sources[0x1e]	358958	1			T1	88		T4	525		T5	109
valid_sources[0x1f]	291590	1			T1	169		T4	498		T5	106
valid_sources[0x20]	360760	1			T1	88		T4	567		T5	93
valid_sources[0x21]	301423	1			T1	191		T4	611		T5	99
valid_sources[0x22]	383657	1			T1	83		T4	559		T5	84
valid_sources[0x23]	300517	1			T1	70		T4	506		T5	101
valid_sources[0x24]	311356	1			T1	42		T4	499		T5	136
valid_sources[0x25]	282696	1			T1	71		T2	1053		T4	527
valid_sources[0x26]	339408	1			T1	146		T4	545		T5	140
valid_sources[0x27]	313357	1			T1	112		T4	511		T5	115
valid_sources[0x28]	334083	1			T1	92		T4	559		T5	144
valid_sources[0x29]	322435	1			T1	101		T4	515		T5	100
valid_sources[0x2a]	317748	1			T1	50		T4	532		T5	100
valid_sources[0x2b]	371446	1			T1	109		T4	518		T5	75
valid_sources[0x2c]	319722	1			T1	34		T4	523		T5	130
valid_sources[0x2d]	329272	1			T1	60		T4	516		T5	92
valid_sources[0x2e]	305988	1			T1	208		T4	533		T5	89
valid_sources[0x2f]	317663	1			T1	57		T2	4130		T4	473
valid_sources[0x30]	316117	1			T1	109		T4	537		T5	128
valid_sources[0x31]	375863	1			T1	80		T4	531		T5	135
valid_sources[0x32]	285186	1			T1	297		T4	585		T5	115
valid_sources[0x33]	300503	1			T1	46		T4	489		T5	113
valid_sources[0x34]	315174	1			T1	151		T4	528		T5	81
valid_sources[0x35]	389194	1			T1	50		T4	511		T5	92
valid_sources[0x36]	310853	1			T1	54		T4	545		T5	93
valid_sources[0x37]	380660	1			T1	86		T4	516		T5	103
valid_sources[0x38]	314485	1			T1	105		T4	521		T5	138
valid_sources[0x39]	323994	1			T1	135		T4	528		T5	90
valid_sources[0x3a]	293655	1			T1	105		T4	561		T5	102
valid_sources[0x3b]	317330	1			T1	71		T4	561		T5	96
valid_sources[0x3c]	342049	1			T1	93		T4	555		T5	130
valid_sources[0x3d]	299729	1			T1	75		T4	529		T5	149
valid_sources[0x3e]	317157	1			T1	151		T4	504		T5	113
valid_sources[0x3f]	299093	1			T1	89		T4	474		T5	95
valid_sources[0x40]	310811	1			T1	41		T4	540		T5	139
valid_sources[0x41]	317063	1			T1	48		T4	556		T5	93
valid_sources[0x42]	294823	1			T1	235		T4	515		T5	129
valid_sources[0x43]	314191	1			T1	80		T4	538		T5	106
valid_sources[0x44]	371897	1			T1	139		T4	566		T5	108
valid_sources[0x45]	310590	1			T1	90		T4	528		T5	96
valid_sources[0x46]	347801	1			T1	112		T4	505		T5	99
valid_sources[0x47]	312453	1			T1	156		T4	552		T5	107
valid_sources[0x48]	298499	1			T1	48		T4	548		T5	107
valid_sources[0x49]	278611	1			T1	123		T2	931		T4	530
valid_sources[0x4a]	278961	1			T1	132		T4	539		T5	114
valid_sources[0x4b]	290788	1			T1	127		T4	547		T5	117
valid_sources[0x4c]	279112	1			T1	38		T4	520		T5	112
valid_sources[0x4d]	299399	1			T1	138		T4	519		T5	118
valid_sources[0x4e]	351602	1			T1	25		T4	529		T5	106
valid_sources[0x4f]	316230	1			T1	36		T4	517		T5	105
valid_sources[0x50]	294876	1			T1	167		T2	379		T4	536
valid_sources[0x51]	325624	1			T1	144		T4	518		T5	95
valid_sources[0x52]	299872	1			T1	30		T4	555		T5	142
valid_sources[0x53]	427022	1			T1	86		T2	795		T4	538
valid_sources[0x54]	372278	1			T1	76		T4	558		T5	111
valid_sources[0x55]	378319	1			T1	97		T4	507		T5	118
valid_sources[0x56]	290280	1			T1	39		T4	518		T5	123
valid_sources[0x57]	309287	1			T1	101		T4	529		T5	87
valid_sources[0x58]	286822	1			T1	123		T4	519		T5	102
valid_sources[0x59]	333273	1			T1	101		T4	525		T5	111
valid_sources[0x5a]	280077	1			T1	160		T4	470		T5	121
valid_sources[0x5b]	302854	1			T1	37		T4	512		T5	102
valid_sources[0x5c]	297064	1			T1	141		T4	544		T5	109
valid_sources[0x5d]	324238	1			T1	213		T4	542		T5	110
valid_sources[0x5e]	312605	1			T1	97		T4	530		T5	89
valid_sources[0x5f]	304929	1			T1	47		T4	511		T5	113
valid_sources[0x60]	283008	1			T1	83		T4	531		T5	141
valid_sources[0x61]	273454	1			T1	54		T4	534		T5	137
valid_sources[0x62]	359154	1			T1	14		T4	542		T5	126
valid_sources[0x63]	352969	1			T1	129		T4	565		T5	102
valid_sources[0x64]	321535	1			T1	114		T2	269		T4	543
valid_sources[0x65]	365463	1			T1	70		T4	508		T5	97
valid_sources[0x66]	280189	1			T1	80		T4	532		T5	124
valid_sources[0x67]	301959	1			T1	173		T4	500		T5	110
valid_sources[0x68]	289226	1			T1	68		T2	485		T4	533
valid_sources[0x69]	322988	1			T1	89		T4	529		T5	118
valid_sources[0x6a]	378924	1			T1	89		T4	579		T5	137
valid_sources[0x6b]	359951	1			T1	178		T4	572		T5	117
valid_sources[0x6c]	350033	1			T1	192		T4	540		T5	82
valid_sources[0x6d]	274830	1			T1	29		T4	548		T5	106
valid_sources[0x6e]	299017	1			T1	77		T2	393		T4	555
valid_sources[0x6f]	333473	1			T1	141		T4	483		T5	145
valid_sources[0x70]	287121	1			T1	146		T4	517		T5	106
valid_sources[0x71]	310777	1			T1	131		T4	532		T5	119
valid_sources[0x72]	365859	1			T1	68		T4	519		T5	95
valid_sources[0x73]	296724	1			T1	69		T4	542		T5	100
valid_sources[0x74]	306549	1			T1	131		T4	499		T5	142
valid_sources[0x75]	278056	1			T1	97		T2	261		T4	583
valid_sources[0x76]	295229	1			T1	163		T4	497		T5	124
valid_sources[0x77]	353005	1			T1	159		T4	564		T5	136
valid_sources[0x78]	297502	1			T1	157		T4	541		T5	110
valid_sources[0x79]	307411	1			T1	120		T4	490		T5	110
valid_sources[0x7a]	280787	1			T1	210		T4	538		T5	115
valid_sources[0x7b]	293826	1			T1	40		T4	480		T5	106
valid_sources[0x7c]	298817	1			T1	49		T4	551		T5	109
valid_sources[0x7d]	312762	1			T1	161		T4	558		T5	129
valid_sources[0x7e]	359975	1			T1	4		T4	541		T5	96
valid_sources[0x7f]	319974	1			T1	146		T4	558		T5	92
valid_sources[0x80]	319530	1			T1	71		T4	505		T5	106

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16459590

1

T1

819

T2

957

T3

1

values[0x0]

all_enables

biggest_size

13588558

1

T1

10572

T2

13436

T4

17983

values[0x1]

all_enables

biggest_size

12152005

1

T1

10735

T2

13362

T4

15408