Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43526928

1

T1

3237

T2

4500

T4

71742

full_word

42399060

1

T1

22126

T2

27755

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85925608	1			T1	25363		T2	32255		T3	1
auto[TlIntgErrCmd]	136	1			T37	10		T38	14		T39	9
auto[TlIntgErrData]	115	1			T37	9		T38	7		T39	4
auto[TlIntgErrBoth]	129	1			T37	11		T38	9		T39	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34367352

1

T1

1666

T2

2534

T3

1

auto[1]

51558636

1

T1

23697

T2

29721

T4

73791

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17829152	1			T1	847		T2	1577		T4	31342
auto[TlIntgErrNone]	partial	auto[1]	25697429	1			T1	2390		T2	2923		T4	40400
auto[TlIntgErrNone]	full_word	auto[0]	16538025	1			T1	819		T2	957		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	25861002	1			T1	21307		T2	26798		T4	33391
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T37	5		T38	5		T39	3
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T37	5		T38	9		T39	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T106	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T104	1		T108	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T37	3		T38	2		T39	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T37	6		T38	4		T39	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T105	1		T110	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T38	1		T104	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T37	4		T38	5		T39	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T37	5		T38	4		T39	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T37	1		T39	1		T104	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T37	1		T104	1		T103	1