Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

35771991

1

T1

69066

T2

34323

T3

715539

full_word

35765061

1

T1

57730

T2

28003

T3

762709

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	71536632	1			T1	126796		T2	62326		T3	147824
auto[TlIntgErrCmd]	118	1			T39	2		T40	7		T41	7
auto[TlIntgErrData]	141	1			T39	3		T40	3		T41	10
auto[TlIntgErrBoth]	161	1			T39	5		T40	10		T41	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28613927

1

T1

51519

T2

25373

T3

605224

auto[1]

42923125

1

T1

75277

T2

36953

T3

873024

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14786850	1			T1	25928		T2	12842		T3	305983
auto[TlIntgErrNone]	partial	auto[1]	20984760	1			T1	43138		T2	21481		T3	409556
auto[TlIntgErrNone]	full_word	auto[0]	13826890	1			T1	25591		T2	12531		T3	299241
auto[TlIntgErrNone]	full_word	auto[1]	21938132	1			T1	32139		T2	15472		T3	463468
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T39	1		T40	2		T41	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T39	1		T40	5		T41	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T96	1		T97	1		T98	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T96	1		T101	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T39	2		T40	1		T41	2
auto[TlIntgErrData]	partial	auto[1]	65	1			T39	1		T40	2		T41	6
auto[TlIntgErrData]	full_word	auto[0]	8	1			T41	1		T98	2		T99	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T41	1		T101	1		T103	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T39	3		T40	1		T41	4
auto[TlIntgErrBoth]	partial	auto[1]	84	1			T39	1		T40	8		T41	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T40	1		T41	1		T98	2
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T39	1		T41	2		T96	1