Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.84	95.88	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390807607	955985	0	0
intr_enable_rd_A	390807607	1937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390807607	955985	0	0
T7	172846	26419	0	0
T8	0	122890	0	0
T9	0	80489	0	0
T19	0	70442	0	0
T39	0	4	0	0
T40	0	6	0	0
T45	0	12	0	0
T47	0	247011	0	0
T48	0	645	0	0
T49	0	420	0	0
T50	217399	0	0	0
T51	200182	0	0	0
T52	27340	0	0	0
T53	31761	0	0	0
T54	332585	0	0	0
T55	191151	0	0	0
T56	1046	0	0	0
T57	100839	0	0	0
T58	4517	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390807607	1937	0	0
T3	153516	44	0	0
T4	347456	0	0	0
T5	98659	0	0	0
T6	287653	0	0	0
T10	0	84	0	0
T11	86399	0	0	0
T12	1136	0	0	0
T13	1293	0	0	0
T15	2481	30	0	0
T21	53928	0	0	0
T34	441311	0	0	0
T39	0	82	0	0
T44	0	20	0	0
T59	0	53	0	0
T60	0	25	0	0
T61	0	40	0	0
T62	0	19	0	0
T63	0	22	0	0